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<-- Previous Next -- > TOPIC: Assign statement in Verilog.
Posted by: mahmed454     7/19/2004 10:14:56 AM     Category: Verilog
Questions posted: 1         Comments Posted: 1
Hi there!
I've just started learning Verilog and have a doubt about assign statement used in it.
if we are writing a code for xor gate like

module(a,b,out);
input a, b;
output out;
assign = a^b;
endmodule

Then what does assign statement do and is it recommended to used assign statement or should use other statement.

Thanks in advance for Answering.

Mubasheer Ahmed.

Posted by: mahmed454     7/20/2004 7:05:50 PM
Comments Posted:1       Questions Posted:1

Thank You verilogic and I really appreciate for correcting syntax.
Thanks.


Posted by: verilogic     7/20/2004 8:43:11 AM
Comments Posted:3       Questions Posted:2

Hi Ahmed!
First, the right syntax for your module is

module(a,b,out);
input a, b;
output out;
assign out = a^b; <--------
endmodule

Assign statement changes the value of "out" at every change of a or b. Use this statement when you want to produce combinational logic in the
RTL level.  




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