cmos inverter

a cmos inverter can have enhancement as well as depletion pull up device. how to choose between the two as far as application is concerned?

Asked By: absjoshi
On: Jul 18, 2004 8:09:35 AM

Comments(3)

i think its the other way round cause in the case of enhancment mode there are 2 ways you can do them: either in the saturation mode or the linear region. In the linear region 2 power supplys are needed. So while deciding which of the 2 ya wanna use in the enhancment, the voltage level that can be reached is vdd- Vt thus the noise margin region is reduced while in depletion region the voltage level is 0 to Vdd. Also if you look at the small signal analysis, the gain of the depletion mode is more than enhancment. other factors like output resistance are also there

Comment By: rskurane
On: Jun 6, 2005 8:21:57 PM

That depends on the power requirements. If it is a lowpower deisng then the designer goes for enhancement mode transistor.

Comment By: kumaranil
On: Aug 12, 2004 2:19:00 AM

I believe its based on whether the designer want Vt to be(for nMOS) +ive or -ive and vice versa for pMOS. In enhancement Vt is +ive for nMOS and -ive (for nMos)for depletion.

Comment By: mfk
On: Jul 24, 2004 7:54:17 PM

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