vlsibank

Log in or Sign up.
Main EDA Embedded Systems ASIC FPGA VHDL Verilog CMOS Semiconductors DSP Mixed Signal Architecture Miscellaneous

<-- Previous Next -- > TOPIC: differences between simulation and synthesis
Posted by: amerahmed     7/12/2004 10:40:58 PM     Category: VHDL
Questions posted: 3         Comments Posted: 0
what is/are the differences between SIMULATION and SYNTHESIS ?

Posted by: geo.ajish     4/25/2009 9:23:14 AM
Comments Posted:1       

-


Posted by: biswajeet80     8/19/2007 7:45:53 AM
Comments Posted:1       Questions Posted:2

what is/are the differences between SIMULATION and SYNTHESIS ?


Posted by: vijaykan     7/13/2004 9:48:20 PM
Comments Posted:10       Questions Posted:5

Simulation is used to verify the functionality of the circuit.. a)Functional Simulation:study of ckt's operation independent of timing parameters and gate delays. b) Timing Simulation :study including estimated delays, verify setup,hold and other timing requirements of devices like flip flops are met.

Synthesis:One of the foremost in back end steps where by synthesizing is nothing but converting VHDL or VERILOG description to a set of primitives(equations as in CPLD) or components(as in FPGA'S)to fit into the target technology.Basically the synthesis tools convert the design description into equations or components


Posted by: knguyen4573     7/13/2004 6:18:55 PM
Comments Posted:2       

Simulation <= verify your design.
synthesis <= Check for your timing




You have to be logged in to be able to post a comment. To login click here. First time? Sign up. It just takes a few minutes to sign up.

Login to access the site

  Username:
  Password:
   Signup Forgot Password?    

Users with most replies

   User
 No. of Replies
266
104
86
76
75
70
63
61
57