verilog code for RAM and FIFO

I want to write verilog code for RAM and FIFO.how RAM is different from FIFO. kindly send a verilog code or a link.

Asked By: arun_singh
On: Feb 21, 2006 11:26:35 AM

Comments(16)

hi friends .....i need to write code for an image noise removal technique.....for that i need to convert the image(grey scale image) into pixel values and then store the image in a set of registers and after that i need to access the registers in such a way that i should compare the pixel values with a 3x3 mask and perform de-noising on the noisy pixel.....after the removal of noise the new pixel value should replace the old pixel value and the 3x3 window should move to the next pixel for the same operation done on the previous pixel.......friends kindly give me some idea so that ican proceed with further coding.....also give idea how to convert image pixels into verilog code inputs

Comment By: praneeth8727
On: Sep 19, 2010 1:07:24 PM

Hi friends... I want asynchronous 128 byte FIFO code with ctrl signals(half full,full,empty).

Comment By: edwinsingh
On: Jun 10, 2010 10:38:37 AM

i want to receive data from UART and store it in a RAM/FIFO for transmitting at a higher rate. which one is preferrable?? and how would i be able to work it out??

Comment By: zeek
On: Jan 16, 2010 1:05:49 AM

hi, first u need to know how much amount of data to be stored,whether its synchronous or asynchronous. In case when it is asynchronous u got to declare clocks with different frequencies. to help u i am sending the code for asynchronous ram module module i2c_sp_ram( //Inputs clk, //clock wr_en, //write enable rd_en, //read enable addr, //address data_in,//data in //Output data_out//data out ); //Parameter Declaration parameter DEPTH = 8; //depth of FIFO parameter ADDR_BUS_WD = 1>>DEPTH; //Address bus width parameter DATA_BUS_WD = 8; //data bus width //Inputs Declarations input clk; //Clock input wr_en; //Write Enable input rd_en; //Read Enable input [ADDR_BUS_WD-1:0] addr; //Address Width input [DATA_BUS_WD-1:0] data_in; //Data Input //output Declarations output [DATA_BUS_WD-1:0] data_out; //Data Output //reg Declarations reg [DATA_BUS_WD-1:0] mem [DEPTH-1:0];//Memory reg [DATA_BUS_WD-1:0] data_out; //Data Output //Generation of data_out always @(posedge clk) begin : READ_GEN if(rd_en) data_out <= mem[addr]; end //Generation Writing data into memory always @(posedge clk) begin: WRITE_GEN if(wr_en) mem[addr] <= data_in; end endmodule

Comment By: raghu_77
On: Feb 25, 2009 6:22:47 AM

hi, I got some good infromation by above discusion.. I need help to write code for ful duplex data transfer between two modules. one module contains FIFO and the other is reader and writer. thanks in advance.. -always_learn

Comment By: always_learn
On: Sep 26, 2008 4:33:41 AM

hi, i am in need of SDRAM verilog code. please send me the code....

Comment By: dineshvlsi
On: Jul 13, 2007 1:50:29 AM

halo saravanan, nice to c u here even if u a for loop in fifo it will synthesize i hav tried it. Lets discuss some new keywords in verilog

Comment By: ramanan.d
On: Jun 12, 2007 3:42:50 AM

hai saravanan_s what u r wrote fifo code has some problems.because you take assign Full=(wrptr > 4'b1111)?1'b1:1'b0; if u take like this, suppose at same time we reading from fifo so we have some memory in fifo.

Comment By: ssssurya
On: Mar 26, 2006 11:15:45 AM

how to calculate fifo depth when wrclk is 2304khz and read clk is 3072 khz.data

Comment By: ssssurya
On: Mar 26, 2006 11:11:38 AM

Hi Saravanan, Can you please provide just a little bit of explanation about the RAM code that you posted earlier. Thanks, Anu

Comment By: anusha.t
On: Mar 23, 2006 4:59:37 PM

saravanan_s: i want to write a fifo too,and thank you for your code. that fifo is ok when depth is 8 or 16, but what happens if i want to write a fifo of 8k depth?

Comment By: bigcrop
On: Mar 14, 2006 10:14:39 PM

any question u want.ask me

Comment By: saravanan_s
On: Mar 3, 2006 8:35:52 AM

for synthesis purpose i had removed for loop

Comment By: saravanan_s
On: Mar 3, 2006 8:35:11 AM

this is not static ram. this is single port ram

Comment By: saravanan_s
On: Mar 3, 2006 8:32:27 AM

first of all you need to consider what is the action you want to do in ram, weather is tht read or write then is it distributed or block, and also is it synchronous or asynchronous then only we can help out u, anyways i'll try to post few combinations of the above. as you can see the ram and fifo are for storing data the basic difference stands in their names itself ram -- random access memory you can read write randomly data in any memory location you want fifo - first in first out you are suppose to write the data shifting the previous one upward then writing in the first location all the time and then retrieving in the same fashion there is no randomaized access in this type of memory. if anybody can give more accurate answer its much appreciated as iam newbee for this design area.

Comment By: crash2ash
On: Feb 28, 2006 3:02:53 AM

i also want to write the code....popuri

Comment By: popuri
On: Feb 24, 2006 1:07:28 AM

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