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<-- Previous Next -- > TOPIC: I need VHDL code for traffic light controller
Posted by: unsubscribed    7/1/2004 7:03:47 AM     Category: VHDL
After reset, the lights along Orchard Rd should be green and that along Somerset Rd should be red. The traffic light at this junction will follow the following rules:
     
a)The lights will not change unless a car is    waiting for the lights to change to green at either roads.

b)If there is a car waiting in front of the red light, the lights will change after a preset interval.

c)The lights should never be green in both direction.To avoid this ensure that when the lights change, both lights should be momentarily red before one light turns green.

d)Lights changing from green to red will have first to turn ember before turning red.Lights going from red to green will not turn to ember before turning green.

Posted by: anuchit     3/2/2005 10:34:47 PM
Comments Posted:3       

--------------------------------------------------------
-- added to make below compile
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------
ENTITY traffic_light IS
 PORT(sensor : IN std_logic;
      clock : IN std_logic;
      red_light : OUT std_logic;
      green_light : OUT std_logic;
      yellow_light : OUT std_logic);
END traffic_light;

ARCHITECTURE simple OF traffic_light IS
  TYPE t_state is (red, green, yellow);
  SIGNAL present_state, next_state : t_state;
BEGIN
  PROCESS(present_state, sensor)
  BEGIN
     CASE present_state IS
        WHEN green =>
           next_state <= yellow;
           red_light <= '0';
           green_light <= '1';
           yellow_light <= '0';
        WHEN red =>
           red_light <= '1';
           green_light <= '0';
           yellow_light <= '0';
           IF (sensor = '1') THEN
              next_state <= green;
           ELSE
              next_state <= red;
           END IF;
        WHEN yellow =>
           red_light <= '0';
           green_light <= '0';
           yellow_light <= '1';
           next_state <= red;
     END CASE;
  END PROCESS;

  PROCESS
  BEGIN
     WAIT UNTIL clock'EVENT and clock = '1';
     present_state <= next_state;
  END PROCESS;
END simple;



Posted by: asicalex     7/3/2004 2:16:16 AM
Comments Posted:2       

Just write some VHDL code for a simple state machine and implement what you described above.  I would use two processes..one for the comb logic and the other for the sequential (state machine).




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