Transistor fingering

hi.. Fingering of MOS gate is done taking many factors in consideration. Basically it is done when u have a large transistor with big value of "w",and u want to fit it in ur layout of given hieght and width. for example if i have a transistor whose w=100micron, and my layout can fit max w=10micron, then i will finger this transistor into 10 equal fingers In Standard Cell design, if a transistor crosses its predifened max size, then it is fingered. Sometimes it is left the the layout engineer to deicde how many fingers he wants to do as per his convience, or sometimes the ciruit designer specifies the required number of fingers. In Anolog designs there is still lot of funda on the flow of current,gate capaticance, diffusiion capaticane so and so forth hope this will help.. regards Vasim

As far as ive studied n understood Fingering is done b cos d cell height is fixed.So if the width of say a p mos transistor is too large then v have to fold the gate n share a common terminal.Just a sharing business is done over here.This is the concept of digital fingering.I dont have an idea abt Analog concept

no it is used mainly to reduce the resistance offered by the poly..and also it reduces the source and drain juction cap