delays in verilog

1. how to synthesise delay using verilog or vhdl? i think using buffers if so tell me how?

Asked By: karthik_988
On: Sep 10, 2005 9:03:36 AM

Comments(2)

delays cant synthesize only in tb we can synthesize

Comment By: sricharan
On: Sep 6, 2010 5:03:34 AM

I think delays cannot be sybnthesized.FRONT END ppl have a rough approx. abt the delays and the technology (of the CMOS trans)behind that.after netlisting it is upto circuit design eng. who optimizes this.

Comment By: venkateshr
On: Sep 16, 2005 9:17:15 AM

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