duty cycle change

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Posted by: gaurav72 8/27/2005 4:30:29 AM Category: CMOS
Questions posted: 1 Comments Posted: 0

hi there evrybody,

i joined in just now...
this is a gr8 site for discussion
and so here's question to begin with:

You are given a 100 MHz clock , you have to Design a 33.3 MHz clock with and without 50 % duty cycle?

How will we detect sequence of “1101” arriving serially from a signal line?

How do we detect if two 8-bit signals are same?

answer soon
thanks for ur concern
gaurav

Posted by: mohaddin 9/14/2005 1:07:16 AM
Comments Posted:3 Questions Posted:1

Hi Friends

what is dusty cycle ,
i did'nt get what is this 25% 50% duty cycle
so can anyone explain what is duty cycle and related issues.

Advance Thanks

Posted by: khushin 8/28/2005 7:36:09 AM
Comments Posted:8 Questions Posted:6

hi

1. In first question i have some problem i think with 50% DC i m not getting.

2. It is very simple u have to just draw state machine so u need s0,s1,s2 and s4 four states. also u can take fifth state if u have to detect sequence only once.
give me your email i will send u state diagram.

3. Third one is very simple u have to use 2 input XNOR if both bits are same output is high use 8 2 input xnor connect them to and gate.i think 8 input and gate is not avaible u have to use 2 4input AND gates and in final use 2 input AND gates.

thanks and regards.

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