plz answer these interview questions

hello, plz do good to answer the following questions; How do we design a divide by 3 cicuit with 50% duty cycle.? Design a divide by 5 sequential ckt with 50% duty cycle? ·How does the size of pmos pull up transistors affect the SRAM’s performance? ·In sram layout which metal layers would you prefer for word lines and bit lines? ·What is the differnce between testing and verification? ·Why is the transconductance of a BJT greater than that of a mosfet? What technology do we use in cmos… NAND OR NOR? WHY? ·What technology do we use in nmos nand or nor? Why?

Asked By: dhirajpunj
On: Aug 27, 2005 4:25:53 AM

Comments(7)

http://www.xilinx.com/xcell/xl33/xl33_30.pdf for this ...good Design a divide by 5 sequential ckt with 50% duty cycle?

Comment By: sashikun
On: Feb 22, 2012 2:33:59 AM

http://www.onsemi.com/pub/Collateral/AND8001-D.PDF for this.. How do we design a divide by 3 cicuit with 50% duty cycle.?

Comment By: sashikun
On: Feb 22, 2012 2:31:01 AM

Verification is a front end process and testing is a post silicon process. verification is to verify the functionality of the design during the design cycle. Testing is find manufacturing faults. or verification: The process of measuring the behaviour of the system in relation to specific benchmarks. testing: find out the fault in manufacturing

Comment By: sashikun
On: Feb 22, 2012 2:18:06 AM

What technology do we use in nmos nand or nor? Why? technology ---cmos In CMOS technology, nmos helps in pulling down the output to ground ann PMOS helps in pulling up the output to Vdd. NAND is a better gate for design than NOR because at the transistor level the mobility of electrons is normally three times that of holes compared to NOR and thus the NAND is a faster gate. Additionally, the gate-leakage in NAND structures is much lower.

Comment By: sashikun
On: Feb 22, 2012 1:51:46 AM

What technology do we use in cmos… NAND OR NOR? WHY? I guess, nowadays many circuits are implemented using NAND. 1)NAND is a universal gate 2)Low power circuit desing using NAND

Comment By: palam8282
On: Sep 7, 2005 1:15:09 PM

i want to know about the heirarchial synthesis,and let me know as how many levels can have

Comment By: helanin
On: Sep 2, 2005 6:15:00 AM

testing is done after the fabrication but where as verification is done in the design called as formal verification

Comment By: helanin
On: Sep 2, 2005 6:14:23 AM

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