hello,

plz do good to answer the following questions;

How do we design a divide by 3 cicuit with 50% duty cycle.?

Design a divide by 5 sequential ckt with 50% duty cycle?

·How does the size of pmos pull up transistors affect the SRAM’s performance?

·In sram layout which metal layers would you prefer for  word lines and bit lines?

·What is the differnce between testing and verification?

·Why is the transconductance of a BJT greater than that of a mosfet?

What technology do we use in cmos… NAND OR NOR? WHY?

·What technology do we use in nmos nand or nor? Why?