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<-- Previous Next -- > TOPIC: wipro motorola interview questions.plz help!!
Posted by:
chhaya11584
8/27/2005 3:21:08 AM Category: CMOS
Questions posted: 19 Comments Posted: 5
Questions posted: 19 Comments Posted: 5
hi ,
these r interview questions asked at wipro and motorola...plz discuss them as soon as possible..
i have my interview on monday..plz help
1.there is a series combination of : -- pmos---pmos--- pmos----nmos
leftmost pmos is connected to Vdd nmos to gnd and output is taken from between 2nd and 3rd pmos. When an input combination is such that all devices are turned on will the output be pulled up or pulled down?
2.How do u size nmos and pmos transistors to increase the threshold voltage?
3.What happens to delay if add a resistance to the output of a cmos ckt?
4.There r three adjacent parallel metal lines. Two out of phase signals pass through the outer two lines what are the waveforms in the center line. What will be the waveform if signal in outer lines are in phase with each other?
5.What happens if we increase the no of contacts or via from one metal layer to the next?
6.In the design of a large inverter y do we prefer to connect small transistors in parallel(thus increasing effective width) rather than make one transistor withlarge width?
7.Suppose u have a combinational ckt between two flip flops(registers)?
What will happen if delay of combinational ckt is greater than clock signal? How will u correct it? (u cant resize combinational ckt transistors)
these r interview questions asked at wipro and motorola...plz discuss them as soon as possible..
i have my interview on monday..plz help
1.there is a series combination of : -- pmos---pmos--- pmos----nmos
leftmost pmos is connected to Vdd nmos to gnd and output is taken from between 2nd and 3rd pmos. When an input combination is such that all devices are turned on will the output be pulled up or pulled down?
2.How do u size nmos and pmos transistors to increase the threshold voltage?
3.What happens to delay if add a resistance to the output of a cmos ckt?
4.There r three adjacent parallel metal lines. Two out of phase signals pass through the outer two lines what are the waveforms in the center line. What will be the waveform if signal in outer lines are in phase with each other?
5.What happens if we increase the no of contacts or via from one metal layer to the next?
6.In the design of a large inverter y do we prefer to connect small transistors in parallel(thus increasing effective width) rather than make one transistor withlarge width?
7.Suppose u have a combinational ckt between two flip flops(registers)?
What will happen if delay of combinational ckt is greater than clock signal? How will u correct it? (u cant resize combinational ckt transistors)
1.0001 and op depends on the sizes or simply depends on the resistances of mosfets.cant comment without that.
2.Vm=(Vdd-modulus(Vtp)+(sqrt(N/P))Vtn)/(1+sqrt(N/P))
N=Kn'w/l similarly for P
3.delay increases due to RC
4.
5.diffusion capacitance increases and resistance too
6.use of fingers facilitates in sharing the drain or source of the parallel trans. so diffusion capacitance is reduced hugely
7. one way is to skew the clock.so that setup time is met.hold time is met due to the delay of combi.skew shd be appropriate so that both violations are averted.
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