see following quesiton asked in interview

4ip or can be done with 3 2X1 mux i presume.connect ip A to i0 and B to select and i1 similarly do with c and d .similarly do another with ip being outputs of these two mxes.

hi, I am just giving the hints. 1)Take a 1x2 decoder with MSB bit(say "A") as its input.Then take this decoder's output as enables to two 1x2 decoders where these two decoders as having the next MSBbit(say "B") ..... 2)This you will get when you pass the given input "clk" signal through a "D flip-flop". So draw a "D-flip-flop" using combinational logic.(This you will find in any Digital electronics book). 3)For this you need 4, 2X1 Muxes.Let A,B,C,D be the inputs of the Or gate with "A" as MSB and D as LSB. Now take a 2X1 Mux and connect "D" as its select input when this select input is zero send "0" to the mux output when the select input is "1" send logic "1" to its output. Now connect this Mux output as input(i.e0th input of 2nd mux) to the 2nd Mux whose select input is "C" when this is "1" send "logic1" as its output ,when the select input is zero send previous mux (i.e 1st mux output through this Mux) now connect this 2nd Mux output as "0th input" of 3rd Mux and repeat the same thing ... 4)Reflected code means gray code. 5) Use DMorgan's Therom... 6)Prove this for 2-input logic gates By taking one of the inputs as select input. 7)I dont Think you will get such a clock with "50% DUTY CYCLE". 8) initial clk=1; always #10 clk=0; #30 clk=1; Thanks & Regards, krs...