plz help!


1can anyone plz guide me how to obtain a 3/2 clock? 2how can we use FET as acapacitor? 3how do slope in transition period of a CMOS inverter's VTC depend on Wn &Wp?wen do it ioncreases & wen decreases?

Asked By: richie
On: Jul 13, 2005 3:48:34 PM

Comments(4)



In order to obtain a 3/2 clock, you use first get the divided by three version of the clock and then xor that clock with a delayed version of the clock.This is basically a clock doubler circuit.By adjusting the dealy you can control the duty cyle of the 3/2 clock.Think this should work. I think we can do it using FSM,but I tried and was not able to. Bye
2. short the source and drain. This is one end of the cap. The other end of cap is the gate. The gate oxide is the cap. c = EA/d d is the gate oxide thickness. A = l*w is the area of the gate oxide. One is constant for the technology (0.13, 0.18, 0.24 micron). The other can be varied based on the mos size.
3.basically the slope is voltage bet. vdd-vt to vt by the voltage at the ip during this tenure. this is the slope during transition( approx. saturation). nmos being sized more than pmos will provide low resistance bet op and gnd so op will be low even for low vip so the slope will be more and the other way for pmos being sized more. bye
2.parasitic cap are used 3. i think it depends on their relative sizes.it is a constant for a ratio.if u size nmos more then slope will be more and if pmos sized more slope will be low.imagine mos to be either current sources(sat) and resistors at triode.and the current is prop to size
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