internal node capacitances in cmos

hi somebody plz answer the following: 1. a)In a 2-input NAND implemented in cmos, high to low prop delay depends on the initial state of internal nodes. WHY? (Upper nand gate is driven by input A and is named M1) b)the worst case happens when the internal node between M1 amd M2 is charged upto Vdd-Vtn which is ensured by pulsing the A input from 1 to 0 to 1while B goes only from 0 to 1. HOW? c)why All internal nodes must be charged to Vdd-Vtn before the inputs are driven high ?

Asked By: chhaya11584
On: Jul 11, 2005 8:14:49 AM

Comments(2)

a small change c)u cant afford to lose the cahrge guys

Comment By: venkateshr
On: Jul 14, 2005 2:15:06 AM

hi chaya, Vt= vt0+ K.(sqrt(K1+Vsb)-sqrt(k1)).increment in vt and this increment is called body effect.any basic mos book has treatment on this irritating and friendly effect. c)this is done in dynamic cmos where u can afford to lose the charge at the op cap. bye

Comment By: venkateshr
On: Jul 13, 2005 2:02:13 AM

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