prop delay of ff/ -ve setup and hold time

hi, i have a problem: plz help!! What is meant by the following statement: The state time of SR latch depends solely on prop delay Tpd of the 2 nor gates. The input transition at S, R should be done at not less than 3Tpd What is transient switching speed? Plz explain theoratically? What is –ve set up time and where is it encountered ? is there any site or book where i can relevant details?

Asked By: karthik99
On: Jul 10, 2005 10:37:44 AM

Comments(2)

hi i think that shd be 2tpd and not 3tpd since the second propagation itself confirms the logic of the feedback.do correct me if i am wrong.

Comment By: venkateshr
On: Jul 13, 2005 1:57:29 AM

hi karthik, setup time is the time taken by any sequential ckt to store the logic.the max time taken by the SR will be 2tpd. S=1 and R=0 assume. !Q=0 1 nor delay. Q=1 1 nor delay. again Nor gate connected to S shd be supplied by 1(Q) which shd be there for min. period which equals prop delay of nor gate to make !Q 0 even if s changes to 0 so that 1 nor delay. so totally 3 nor delays. 1st nor to 2nd and 2nd to first and then first to second. on clock skews u can find those -ve tsu and holds. I have one small pdf which i got when i was searching for something other.if u want i will send you. hope the expln. clarifies you karthik .if not i am ready to tell u. bye

Comment By: venkateshr
On: Jul 12, 2005 2:05:51 AM

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