adder program code is available here..
also this link teach you about 2 types of component declaration methods..
http://vhdlguru.blogspot.com/2010/03/usage-of-components-and-port-mapping.html

refer above

HI HILUV
I SENT YOU THE CODE FOR 8 BIT FULL ADDER BUT I DO NOT KNOW IF IT IS FOR SERIAL OR PARALLEL FULL
ADDER.ALSO I NEED 16 BIT SERIAL FULL ADDER.CAN YOU HELP ME?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fad is
  Port ( a : in std_logic;
         b : in std_logic;
         ci : in std_logic;
         S : out std_logic;
         co : out std_logic);
end fad;

architecture Behavioral of fad is

begin
process(a,b,ci)
begin
s<= a xor b xor ci;
co<= (a and b ) or (ci and b ) or (a and ci ) ;
end process;

end Behavioral;




library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
  Port ( a : in std_logic_vector(3 downto 0);
         b : in std_logic_vector(3 downto 0);
         c : in std_logic;
         s : out std_logic_vector(3 downto 0);
         co : out std_logic);
end top;
architecture Behavioral of top is
     component fad
             port( a,b,ci : in std_logic;
                  s,co: out std_logic);
     end component;
  signal c_s:std_logic_vector(3 downto 0);
  signal co_s: std_logic;
begin

  x1: fad
      port map(a => a(0),b=>b(0),ci=> c, s=> s(0), co=> c_s(0));

  x2: fad
      port map(a => a(1),b=>b(1),ci=> c_s(0), s=> s(1), co=> c_s(1));

x3: fad
     port map(a => a(2),b=>b(2),ci=> c_s(1), s=> s(2), co=> c_s(2));

x4: fad
     port map(a => a(3),b=>b(3),ci=> c_s(2), s=> s(3), co=> c_s(3));

co<= c_s(3);

end Behavioral; R.PLEASE CHECK IT AND TELL ME!