hold time in digital circuits n some bjt prob

Hi richie, 1.we use setup time for frequency calculation.we consider all the contamination delays of combi and seq ckts and skew (if) for hold time calc. 2.for max freq. we consider setup time and delays (as usual) and skew(if). 3.in saturaion collector will be at .02 volts higher than emitter and that is constant .it is like having a diode drop thru a resistor and the current depends on the supply and the resistance.hope the word saturation is taken in its sense. 4.in reverse sat.(i suppose) the emitter and collector are swapped which is not good for driving current and the saturation here is what u called as reverse sat. this is not recommended since the current gain of this config. (reversal of emitter and collector ) is poor so not recommended. 5.in wired op just see the output transisto of the two wired gates.except ECL the op will be anded of the two ops.bcause even if one transistor is shorted to gnd the other will also so u have op=1 if and only if both the ops are 1.in ecl the voltage range is negative say -.8 for logic 1 and -1.8 for logic 0 so if u tie those two they will settle for lowest voltage(consider the modulus)which is -.8 (1) so ored op.