TRANSISTOR SIZING/ PULLUP RESISTENCE OF nand

hi everyone, i just joined this group. thought might get my doubts cleared from all u wonderful design engineers. plz help me through! a)If we implement the fuction NOT[D+ A(B+C)] in cmos and consider transistor sizing wrt to an equivalent inverter how will we size pmos transisitors ? What is the underlying funda/concept regarding resistance of the pmos circuit and current carried by each transisitor? b)For a combinational circuit implemented in cmos y does the noise margin depend upon the input pattern, say for the ckt not[D+A(B+C)]? c) PLZ read the following statement (in parts): In a 2-input NAND implemented in cmos high to low prop delay depends on the initial state of internal nodes. WHY? (Upper nand gate is driven by input A and is named M1) Next, the worst case happens when the internal node between M1 amd M2 is charged upto Vdd-Vtn which is ensured by pulsing the A input from 1 to 0 to 1while B goes only from 0 to 1.HOW? All internal nodes must be charged to Vdd-Vtn before the inputs are driven high. Why so? D)For a nand implemented in cmos a linear increase in no of pmos transistors doe not inc the pull up resistance? STATED IN Rabaey book Of course, in the worst case when only one input to pmos is low the resisitence will remain unchanged but if we have all inputs low( that is the case of strongest pull up) I think the resistance will dec with inc in pmos transistors as all of them are in parallel. PLEASE COMMENT! THANKS IN ADVANCE