self loading in CMOS

5) In the depletion load NMOS, both the gate and the source arer connected together. Thus change in the source and the subsrate voltage causes Vbs and thus body effect

thanks venkatesh it really clears my doubts thanks a lot

HI, 1. velocity saturation is pushing the electroncs to its maximum speed (i think 10^5 mts/sec).beyond that it wont .thereby the current=dq/dt suffers from non-increment problem even if u increase the V. V=Mobility*E/(1+E/Ec) where E is electric field (V/d) and Ec is critical elc. field (max). saturation mode on the other hand is due to Vdsbeing equal to Vgs-Vt that is pichoff . 2.self loading is nothing but op capacitance(due to drain depletion cap and miller cap.) at the op. if u increase w/l more then the op capacitance is also increased.this is self loading.this means a gate has to drive more to charge or discharge a large capacitor which is the result of making the gate a strong driver like see-saw.morever it offers more load to the next gate too. sizing a gate is goaded by many guidelines taking account of all gates in the path.ppl call this as logical effort. 3.we shd have odd no of inverters to have oscillations.morever the chain shd consist of some min no of inverters to have oscillations say 5 or more before that it would make the op at Vdd/2 like one.u cannot have an oscillator with one inverter because if u tie up the op and ip it would result not in oscillations. 4.Cgb is almost constant and is WLCox where Cox is capacitance ofd oxide/area.Cdb and Csb are variable since they are due to the depletion layer(reverse biased diode (varicap))formed and that depends upon the voltage u apply.the dependence is guided by a non linear equation. 5. i donno. the first 3 are copied from the answer to ur question . chaya u overlooked that since u didnt categorise the question. bye