Latch and set up / hold time


Hello all, Does latch sometimes have the set and hold time constraints like a flop? Since flop depends on the clock edge for transfer of data and latch depends on the active gate signal ? Inspite of this I came across a document where the set up and hold time of latch is calculated using timing analysis ? Can someone plz clearify the doubt abt latch and set up / Hold time requirements ?

Asked By: bobby1277
On: Jun 9, 2005 1:23:23 AM

Comments(3)



parag there is a f/b loop . i dont think it will act as a flop
hi venkatesh, dint get what u explained above can u plz elaborate on it? regards
this was explained .since latch works for a pulse instead of an event it cannot be said since if it misses the first edge it will work after sometime and you expect the data (which is at the ip at that time ) to be latched and that occurs. the problem comes if the data changes within tsu or just b4 the falling edge of latch which latches if clock=1. i think u got that.same with hold time. remember this ff is a latch with very short clock period so that no two data latched at one go.so latch and ff have those but latch is immune to those violations under most of the circumstances.bye
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