Query related to CMOS Inputs - Thanks Rohit

Hi Rohit, Thanks a lot for such an explanation. This is my inference. The signal which has higher frequency should be connected towards the ground and the signal with lower frequency should be connected nearer to the output. If we connect it the other wise it would increase the delay. Tell me whether this inference is correct??? Thanks once again. Jai

Asked By: jai_236
On: Jun 5, 2005 10:47:20 AM

Comments(4)

Hi Rohit, Praveen, Venkatesh. Thanks a lot for the clarification. Jai

Comment By: jai_236
On: Jun 7, 2005 10:27:52 AM

Guys , yeah correct the signal with higher frequency shd be placed near the gnd. but not always .u remember one question asked by our friend that A & B with A toggling twice that of B .here if u asssume that the ckt would be cramped for time if A is near gnd. think over and mail me (post ).i explained that frend reg that , assuming B to be at op and when B =1 and A=0 and B=1,A=1 will flaw the ckt if it is pushed for time.think over this one.

Comment By: venkateshr
On: Jun 7, 2005 1:16:51 AM

From power point of view the input with higher frequency should be placed near the output because : If the input with higher frequency is place near Vdd or ground it will charge or discharge every time it is switching on, which is not good since this switching might be futile as it might not affect the output (depending on whether it is assuming dominant or non-dominant value /what value the other input assumes).

Comment By: praveen_sam
On: Jun 6, 2005 11:12:10 AM

Hi, what you think is right -rohit

Comment By: rskurane
On: Jun 5, 2005 5:58:17 PM

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