Query related to CMOS Inputs


Hi, This is a question which was posted sometime back. Among the signals A and B, with A having higher frequency than B, which one should be connected nearest to the output to the inverter. Can u please explain in detail regarding this. Thanks in advance.

Asked By: jai_236
On: Jun 3, 2005 8:37:42 AM

Comments(2)



both are correct shd be the apt way to answer the question since both has some disadvantages and among the two when u consider the timing A near the op is better since it will have shorter operating time(A=1) so it shd not be bothered with much capacitance to discharge but this also has disadvantage if A=1 and sometime later B=1 and sometime later A=0 happens. in short if we have two inputs A and B like a clock and clock/2 frequency then A at op is better .clarify me if iam wrong.i think u got what i meant.
OK,(Draw the diagram as we go along) Consider a stack of NMOS transistors(one above each other). Remember that each transistor has its own internal capacitance associated with it. So if you have A, B, C transistors one above another(A is at the bottom and C is at the top) the internal capacitances are Ca, Cb and Cc respectively. Now we also have a load capacitance Cload at the output(this is connected at the drain of transistor Cc). Now the question is that if you have a signal at A arriving later than the signal arriving at B which one should be placed at the output?. If you connect B to the output then obviously the time needed discharge the internal capacitances(Ca, Cc) and the load capacitance(Cload) would result in reduction of speed(longer delay) as compared to A transistor connected to the output(since it only has to discharge the load capacitance Cc). Remember the equation is 0.69 RC. I hope you get it. rohit
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