what is a race condition

for eg: Consider a SR FF with a clock. If both of your SR inputs are 0 then both the outputs Q and Qbar are low and high resp.(clock is either low or high). Now when both of the inputs are high and the clock is also changing from low to high then both the outputs (Q and Qbar)are high.i.e final state cannot be determined ahead of time. this is called the race conditon. this is a problem of SR FF. so to remove this JK FF came into the picture. so consider what your question with the above case output of the combinational logic changes from low to high== clock of the FF. and inputs of your FF(S and R) are also high