cmos nand gate

hi, i have been asked in an interview that "if we have two square wave signals, one of which toggles twice as the other one i.e., signal A has higher double the frequency to that of signal B. Which signa(A or B) should be given to the the Nmos gate which is close to the ground of CMOS NAND gate to ensure the high performance of the NAND gate" ur response would be greatly appreciated....

Asked By: mai3
On: May 19, 2005 5:59:48 PM

Comments(3)

i am extremely sorry guys please ignore the above two as i took the other way.actually i intended that A shd be kept near the op so that there wont be any body effect problem.the case can be treated as delay of A wrt to B when they are logic 1.correct me if iam wrong.Regrets for the cause.bye,

Comment By: venkateshr
On: May 20, 2005 4:46:46 AM

there is one small correction that B will not face half the probability but b will face nothing.remember if the node capacitance is huge huge or B delays A then B shd be kept atop A.

Comment By: venkateshr
On: May 20, 2005 3:06:58 AM

so your op shd reflect upon the ip of higher frequency which is A.I think A shd be connected near to the gnd one. explanation : A changes twice the no of times as B if B is connected near to gnd then the discarge time will be more since A will rise from 0->vdd but will face a source voltage (depending upon the resistance of B)in the parasitic capacitor at source of A.if A is connected near to gnd then there is optimization because B will face the problem with half the probability of A.if not clear give your mail id mai3 .i can substantiate my statement. bye

Comment By: venkateshr
On: May 20, 2005 1:47:52 AM

You have to be logged in to be able to post a comment. To login Click Here. First time? Signup It just takes a few minutes to sign up.

Members with Most Replies

Find Job Openings

Indeed jobs