interview question

Icewind, The equations for the setup and hold margin are: Setup Margin = Tcycle(min) - Tco(max) - Tsu - Tflight(max) - Tskew - Tjitter Hold Margin= Tco(min) + Tflight(min) - Thld - Tskew So accoridng to what you said Skew= T(b)- T(a) which is positive(clock at destination reaches later than source). So if the skew is more then that reduces the setup margin and not increases it. So since the setup time determines the maximum frequency you want your skew time to be as low as possible(that is both clocks should be in phase). For the hold margin you ideally want the hold marign to be zero. So in this case if skew is more then that will reduce the hold margin. I hope what I am saying is right, what do you guys think?

Hello Madhusudhan, I dont know the correct answer for ur qn.So I'm not putting up my wild guessworks.But I will advice to put more interview qn:s from ur personal experience or thro friends' experiences so that others who looks this site for guidance/interview qns will be benefitted.So keep doing ur good work.Bye.Regds.Tom

Hey, icewind, i have got very big doubt that whether the skew belongs to combinational logic or just sequential logic?? and also how about setuptime and hold time?? will they belong to comb or sequential logic??

Hi, Clock skew can be interpreted in this way.A tactic for achieving a greater clock speed which is not possible otherwise.Anyway here you will get the op late as with large clock periods but this is not for all .for some short paths the op can be extracted earlier by forcing a lesser clock period clock.The words of icewind explains that better.

For a circuit Source Register ---- Combinational Logic ---- Destination register, Clock skew (clock at destination arrives later than source register ) affects the circuit as: 1. It increases setup time at the destination register 2. It decreases the hold time at the destination register. So, if the combinational logic is very small, then clock skew is a disadvantage. If the combinational logic is very large, then the clock skew can work to an advantage. In large combo blocks like multipliers / ALUS, clock is skewed at destination clock to allow the huge combo logic to be executed and still meet setup w.r.t destination register.