how to implement LUT(lookup table) in Verilog

Hi all, I'd like to find out how to implement LUT in Verilog. I've seen two ways to do so: 1) using CASE statement and 2) assigning the values of LUT in "always @(posedge clk)" block. I thought it might also be possible to 3) have a memory in the size of LUT and assign each values from the beginning, then refer to(or copy) its values by indexing(or addressing). I'd like to find out the diffeerences among these three possible ways and know which is the best way to implement LUT. Below is examples of the three ways. Please let me know which method I'd better choose. thanks in advance! // 1) case statement reg [7:0] LUT [0:15]; always @ (addr) begin case (addr) 0: out = 8'h0F; 1: out = 8'h00; 2: out = 8'h01; . . . endcase // 2) assigning in "always @(posedge clk)" block always@(posedge clk) begin LUT[0] = 8'h0F; LUT[1] = 8'h00; LUT[2] = 8'h01; . . . // 3) having memory for LUT and referring by idexing reg [7:0] LUT [0:15] = {8'h0F,8'h00,8'h01,...};