NAND

Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

Asked By: jay_bits
On: Apr 29, 2005 1:42:30 AM

Comments(2)

Hi, Venkateshr thanks a lot for clearing my doubts....

Comment By: jay_bits
On: Apr 29, 2005 4:22:54 AM

Hai, The nmos ips shd be placed in descending order (down to gnd)i.e ip with largest delay shd be near the op and with the shortest near the gnd. Reasons: 1.Body effect of transistors slows the process of sinking.(if shortest delay ip nearer to op). 2.the largest delay ip NMOS has to pull down all the parasitic capacitors of shortest delay nmos if u assume the longest delay transsistoer near to gnd. hope u got that.

Comment By: venkateshr
On: Apr 29, 2005 2:35:14 AM

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