backpropagation network

hi could you send the code for sigmoid? thanks.

Dear Talous, The network I am using has two inputs and one output. I am also using a linear activation function (I do have the sigmoid activation function component - will be send upon request -). To make it easy for you, here is a simple code for the backpropagation algorithm. When compiled, it will ask you for components such as mac or mol (pipeline multiplication of three inputs), moc (same as mac but with three inputs instead of two)... You will find all the component in the code above. --------------------------------------------------------------------------- --Déclaration des librairies LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; USE work.projet.all; --Déclaration de l'entité ENTITY supervisor IS PORT ( e1 : IN std_logic_vector(length downto 1); -- first input e2 : IN std_logic_vector(length downto 1); -- second input S1 : IN std_logic_vector(length DOWNTO 1); -- adaptation signal (input) clk : IN std_logic; reset : IN std_logic; b : OUT std_logic_vector(length DOWNTO 1) -- Network's output ); END supervisor; --Déclaration de l'architecture ARCHITECTURE behavioral OF supervisor IS SIGNAL bx00,bx10,Yso : std_logic_vector(length downto 1); SIGNAL wa0,wa1,wa2 : std_logic_vector(length downto 1); SIGNAL wb0,wb1,wb2 : std_logic_vector(length downto 1); SIGNAL wc0,wc1,wc2 : std_logic_vector(length downto 1); SIGNAL swa0,swa1,swa2 : std_logic_vector(length downto 1); SIGNAL swb0,swb1,swb2 : std_logic_vector(length downto 1); SIGNAL swc0,swc1,swc2 : std_logic_vector(length downto 1); SIGNAL err,nuu : std_logic_vector(length downto 1); BEGIN b <= Yso; -- Neural network's output --------------------------------------------------------------------------- couche1_1 : neuron PORT MAP (e1=>e1,e2=>e2,w0=>wa0,w1=>wa1,w2=>wa2,clk=>clk,reset=>reset,b=>bx00); couche1_2 : neuron PORT MAP (e1=>e1,e2=>e2,w0=>wb0,w1=>wb1,w2=>wb2,clk=>clk,reset=>reset,b=>bx10); --------------------------------------------------------------------------- couche2_1 : neuron PORT MAP (e1=>bx00,e2=>bx10,w0=>wc0,w1=>wc1,w2=>wc2,clk=>clk,reset=>reset,b=>Yso); --------------------------------------------------------------------------- compute_1 : mol PORT MAP (Sdata_in1=>bx00,Sdata_in2=>wc1,Sdata_in3=>err,clk=>clk,reset=>reset,Sdata_out=>ro1); compute_2 : mol PORT MAP (Sdata_in1=>bx10,Sdata_in2=>wc2,Sdata_in3=>err,clk=>clk,reset=>reset,Sdata_out=>ro2); --------------------------------------------------------------------------- ajust_1 : back_1 PORT MAP (by0=>bx00,by1=>bx10,nuu=>nuu,err=>err,clk=>clk,reset=>reset, awc0=>wc0,awc1=>wc1,awc2=>wc2, wc0=>swc0,wc1=>swc1,wc2=>swc2); ajust_2 : back_2 PORT MAP (e1=>e1,e2=>e2,ro1=>ro1,ro2=>ro2,nuu=>nuu,clk=>clk,reset=>reset, awa0=>wa0,awa1=>wa1,awa2=>wa2, awb0=>wb0,awb1=>wb1,awb2=>wb2, wa0=>swa0,wa1=>swa1,wa2=>swa2, wb0=>swb0,wb1=>swb1,wb2=>swb2); --------------------------------------------------------------------------- PROCESS(clk) BEGIN IF (clk'EVENT AND clk = '1') THEN IF (reset = '1') THEN wa0 <= xnuu; wa1 <= xnuu; wa2 <= xnuu; wb0 <= xnuu; wb1 <= xnuu; wb2 <= xnuu; wc0 <= xnuu; wc1 <= xnuu; wc2 <= xnuu; ELSE wa0 <= swa0; wa1 <= swa1; wa2 <= swa2; wb0 <= swb0; wb1 <= swb1; wb2 <= swb2; wc0 <= swc0; wc1 <= swc1; wc2 <= swc2; END IF; END IF; END PROCESS; END behavioral; ---------------------------------------------------------------------------

which activation function did you used and how did you implement it? thanks

--Déclaration des librairies LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; --Déclaration du package PACKAGE projet IS CONSTANT length : integer := 32; CONSTANT norm : integer := length-1; CONSTANT allzeros : std_logic_vector(length DOWNTO 1) := "00000000000000000000000000000000"; -- Normalisation 0 * 2^norm CONSTANT xnuu : std_logic_vector(length DOWNTO 1) := "00000001010001111010111000010100"; -- Normalisation 1e-2 * 2^norm CONSTANT step1 : std_logic_vector(length DOWNTO 1) := "00000000000000000000000011010111"; -- Normalisation 1e-7 * 2^norm CONSTANT step2 : std_logic_vector(length DOWNTO 1) := "11111111111111111111111100101001"; -- Normalisation -1e-7 * 2^norm CONSTANT lambda : std_logic_vector(length DOWNTO 1) := "00000000111101011100001010001111"; -- Normalisation 0.75/100 * 2^norm CONSTANT notlambda : std_logic_vector(length DOWNTO 1) := "11111111000010100011110101110001"; -- Normalisation -0.75/100 * 2^norm CONSTANT notone : std_logic_vector(length DOWNTO 1) := "11111110101110000101000111101100"; -- Normalisation -1/100 * 2^norm COMPONENT mac PORT( Sdata_in1 : IN std_logic_vector(length DOWNTO 1); Sdata_in2 : IN std_logic_vector(length DOWNTO 1); Sdata_in3 : IN std_logic_vector(length DOWNTO 1); clk : IN std_logic; reset : IN std_logic; Sdata_out : OUT std_logic_vector(length DOWNTO 1) ); END COMPONENT; COMPONENT acm PORT( Sdata_in1 : IN std_logic_vector(length DOWNTO 1); Sdata_in2 : IN std_logic_vector(length DOWNTO 1); Sdata_in3 : IN std_logic_vector(length DOWNTO 1); clk : IN std_logic; reset : IN std_logic; Sdata_out : OUT std_logic_vector(length DOWNTO 1) ); END COMPONENT; COMPONENT mol PORT( Sdata_in1 : IN std_logic_vector(length DOWNTO 1); Sdata_in2 : IN std_logic_vector(length DOWNTO 1); Sdata_in3 : IN std_logic_vector(length DOWNTO 1); clk : IN std_logic; reset : IN std_logic; Sdata_out : OUT std_logic_vector(length DOWNTO 1) ); END COMPONENT; COMPONENT moc PORT( Sdata_in1 : IN std_logic_vector(length DOWNTO 1); Sdata_in2 : IN std_logic_vector(length DOWNTO 1); Sdata_in3 : IN std_logic_vector(length DOWNTO 1); Sdata_in4 : IN std_logic_vector(length DOWNTO 1); clk : IN std_logic; reset : IN std_logic; Sdata_out : OUT std_logic_vector(length DOWNTO 1) ); END COMPONENT; COMPONENT back_1 PORT( by0 : IN std_logic_vector(length DOWNTO 1); by1 : IN std_logic_vector(length downto 1); nuu : IN std_logic_vector(length downto 1); err : IN std_logic_vector(length downto 1); clk : IN std_logic; reset : IN std_logic; awc0 : IN std_logic_vector(length downto 1); awc1 : IN std_logic_vector(length downto 1); awc2 : IN std_logic_vector(length downto 1); wc0 : OUT std_logic_vector(length downto 1); wc1 : OUT std_logic_vector(length downto 1); wc2 : OUT std_logic_vector(length downto 1) ); END COMPONENT; COMPONENT back_2 PORT( e1 : IN std_logic_vector(length downto 1); e2 : IN std_logic_vector(length downto 1); ro1 : IN std_logic_vector(length downto 1); ro2 : IN std_logic_vector(length downto 1); nuu1 : IN std_logic_vector(length downto 1); nuu2 : IN std_logic_vector(length downto 1); clk : IN std_logic; reset : IN std_logic; awa0 : IN std_logic_vector(length downto 1); awa1 : IN std_logic_vector(length downto 1); awa2 : IN std_logic_vector(length downto 1); awb0 : IN std_logic_vector(length downto 1); awb1 : IN std_logic_vector(length downto 1); awb2 : IN std_logic_vector(length downto 1); wa0 : OUT std_logic_vector(length downto 1); wa1 : OUT std_logic_vector(length downto 1); wa2 : OUT std_logic_vector(length downto 1); wb0 : OUT std_logic_vector(length downto 1); wb1 : OUT std_logic_vector(length downto 1); wb2 : OUT std_logic_vector(length downto 1) ); END COMPONENT; COMPONENT neuron PORT( e1 : IN std_logic_vector(length downto 1); e2 : IN std_logic_vector(length downto 1); w0 : IN std_logic_vector(length DOWNTO 1); w1 : IN std_logic_vector(length DOWNTO 1); w2 : IN std_logic_vector(length DOWNTO 1); clk : IN std_logic; reset : IN std_logic; b : OUT std_logic_vector(length DOWNTO 1) ); END COMPONENT; END projet; PACKAGE body projet IS END projet; --------------------------------------------------------------------------- --Déclaration des librairies LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; USE work.projet.all; --Déclaration de l'entité ENTITY mac IS PORT ( Sdata_in1 : IN std_logic_vector(length DOWNTO 1); Sdata_in2 : IN std_logic_vector(length DOWNTO 1); Sdata_in3 : IN std_logic_vector(length DOWNTO 1); clk : IN std_logic; reset : IN std_logic; Sdata_out : OUT std_logic_vector(length DOWNTO 1) ); END mac; --Déclaration de l'architecture ARCHITECTURE behavioral OF mac IS SIGNAL t_out : std_logic_vector(length DOWNTO 1); BEGIN PROCESS(clk) VARIABLE temp : std_logic_vector(length*2 DOWNTO 1); BEGIN IF (clk'EVENT AND clk = '1') THEN IF (reset = '1') THEN t_out <= (OTHERS => '0'); ELSE temp := Sdata_in1 * Sdata_in2; t_out <= temp(length*2) & temp(length+norm-1 DOWNTO norm+1); END IF; END IF; END PROCESS; Sdata_out <= t_out + Sdata_in3; END behavioral; --------------------------------------------------------------------------- --Déclaration des librairies LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; USE work.projet.all; --Déclaration de l'entité ENTITY acm IS PORT ( Sdata_in1 : IN std_logic_vector(length DOWNTO 1); Sdata_in2 : IN std_logic_vector(length DOWNTO 1); Sdata_in3 : IN std_logic_vector(length DOWNTO 1); clk : IN std_logic; reset : IN std_logic; Sdata_out : OUT std_logic_vector(length DOWNTO 1) ); END acm; --Déclaration de l'architecture ARCHITECTURE behavioral OF acm IS SIGNAL temp : std_logic_vector(length*2 DOWNTO 1); SIGNAL t_out : std_logic_vector(length DOWNTO 1); BEGIN PROCESS(clk) BEGIN IF (clk'EVENT AND clk = '1') THEN IF (reset = '1') THEN t_out <= (OTHERS => '0'); ELSE t_out <= Sdata_in1 + Sdata_in2; END IF; END IF; END PROCESS; temp <= t_out * Sdata_in3; Sdata_out <= temp(length*2) & temp(length+norm-1 DOWNTO norm+1); END behavioral; --------------------------------------------------------------------------- --Déclaration des librairies LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; USE work.projet.all; --Déclaration de l'entité ENTITY mol IS PORT ( Sdata_in1 : IN std_logic_vector(length DOWNTO 1); Sdata_in2 : IN std_logic_vector(length DOWNTO 1); Sdata_in3 : IN std_logic_vector(length DOWNTO 1); clk : IN std_logic; reset : IN std_logic; Sdata_out : OUT std_logic_vector(length DOWNTO 1) ); END mol; --Déclaration de l'architecture ARCHITECTURE behavioral OF mol IS SIGNAL temp2 : std_logic_vector(length*2 DOWNTO 1); SIGNAL t_out : std_logic_vector(length DOWNTO 1); BEGIN PROCESS(clk) VARIABLE temp1 : std_logic_vector(length*2 DOWNTO 1); BEGIN IF (clk'EVENT AND clk = '1') THEN IF (reset = '1') THEN t_out <= (OTHERS => '0'); ELSE temp1 := Sdata_in1 * Sdata_in2; t_out <= temp1(length*2) & temp1(length+norm-1 DOWNTO norm+1); END IF; END IF; END PROCESS; temp2 <= t_out * Sdata_in3; Sdata_out <= temp2(length*2) & temp2(length+norm-1 DOWNTO norm+1); END behavioral; --------------------------------------------------------------------------- --Déclaration des librairies LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; USE work.projet.all; --Déclaration de l'entité ENTITY moc IS PORT ( Sdata_in1 : IN std_logic_vector(length DOWNTO 1); Sdata_in2 : IN std_logic_vector(length DOWNTO 1); Sdata_in3 : IN std_logic_vector(length DOWNTO 1); Sdata_in4 : IN std_logic_vector(length DOWNTO 1); clk : IN std_logic; reset : IN std_logic; Sdata_out : OUT std_logic_vector(length DOWNTO 1) ); END moc; --Déclaration de l'architecture ARCHITECTURE behavioral OF moc IS SIGNAL ent : std_logic_vector(length DOWNTO 1); BEGIN moc_1 : mol PORT MAP (Sdata_in1=>Sdata_in1,Sdata_in2=>Sdata_in2,Sdata_in3=>Sdata_in3,clk=>clk,reset=>reset,Sdata_out=>ent); PROCESS(clk) VARIABLE temp1 : std_logic_vector(length*2 DOWNTO 1); BEGIN IF (clk'EVENT AND clk = '0') THEN IF (reset = '1') THEN Sdata_out <= (OTHERS => '0'); ELSE Sdata_out <= ent + Sdata_in4; END IF; END IF; END PROCESS; END behavioral; --------------------------------------------------------------------------- --Déclaration des librairies LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; USE work.projet.all; --Déclaration de l'entité ENTITY back_1 IS PORT ( by0 : IN std_logic_vector(length DOWNTO 1); by1 : IN std_logic_vector(length downto 1); nuu : IN std_logic_vector(length downto 1); err : IN std_logic_vector(length downto 1); clk : IN std_logic; reset : IN std_logic; awc0 : IN std_logic_vector(length downto 1); awc1 : IN std_logic_vector(length downto 1); awc2 : IN std_logic_vector(length downto 1); wc0 : OUT std_logic_vector(length downto 1); wc1 : OUT std_logic_vector(length downto 1); wc2 : OUT std_logic_vector(length downto 1) ); END back_1; --Déclaration de l'architecture ARCHITECTURE behavioral OF back_1 IS BEGIN back1_1 : mac PORT MAP (Sdata_in1=>nuu,Sdata_in2=>err,Sdata_in3=>awc0,clk=>clk,reset=>reset,Sdata_out=>wc0); back1_2 : moc PORT MAP (Sdata_in1=>by0,Sdata_in2=>nuu,Sdata_in3=>err,Sdata_in4=>awc1,clk=>clk,reset=>reset,Sdata_out=>wc1); back1_3 : moc PORT MAP (Sdata_in1=>by1,Sdata_in2=>nuu,Sdata_in3=>err,Sdata_in4=>awc2,clk=>clk,reset=>reset,Sdata_out=>wc2); END behavioral; --------------------------------------------------------------------------- --Déclaration des librairies LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; USE work.projet.all; --Déclaration de l'entité ENTITY back_2 IS PORT ( e1 : IN std_logic_vector(length downto 1); e2 : IN std_logic_vector(length downto 1); ro1 : IN std_logic_vector(length downto 1); ro2 : IN std_logic_vector(length downto 1); nuu1 : IN std_logic_vector(length downto 1); nuu2 : IN std_logic_vector(length downto 1); clk : IN std_logic; reset : IN std_logic; awa0 : IN std_logic_vector(length downto 1); awa1 : IN std_logic_vector(length downto 1); awa2 : IN std_logic_vector(length downto 1); awb0 : IN std_logic_vector(length downto 1); awb1 : IN std_logic_vector(length downto 1); awb2 : IN std_logic_vector(length downto 1); wa0 : OUT std_logic_vector(length downto 1); wa1 : OUT std_logic_vector(length downto 1); wa2 : OUT std_logic_vector(length downto 1); wb0 : OUT std_logic_vector(length downto 1); wb1 : OUT std_logic_vector(length downto 1); wb2 : OUT std_logic_vector(length downto 1) ); END back_2; --Déclaration de l'architecture ARCHITECTURE behavioral OF back_2 IS BEGIN back2_1 : mac PORT MAP (Sdata_in1=>nuu1,Sdata_in2=>ro1,Sdata_in3=>awa0,clk=>clk,reset=>reset,Sdata_out=>wa0); back2_2 : moc PORT MAP (Sdata_in1=>e1,Sdata_in2=>nuu1,Sdata_in3=>ro1,Sdata_in4=>awa1,clk=>clk,reset=>reset,Sdata_out=>wa1); back2_3 : moc PORT MAP (Sdata_in1=>e2,Sdata_in2=>nuu1,Sdata_in3=>ro1,Sdata_in4=>awa2,clk=>clk,reset=>reset,Sdata_out=>wa2); back2_4 : mac PORT MAP (Sdata_in1=>nuu2,Sdata_in2=>ro2,Sdata_in3=>awb0,clk=>clk,reset=>reset,Sdata_out=>wb0); back2_5 : moc PORT MAP (Sdata_in1=>e1,Sdata_in2=>nuu2,Sdata_in3=>ro2,Sdata_in4=>awb1,clk=>clk,reset=>reset,Sdata_out=>wb1); back2_6 : moc PORT MAP (Sdata_in1=>e2,Sdata_in2=>nuu2,Sdata_in3=>ro2,Sdata_in4=>awb2,clk=>clk,reset=>reset,Sdata_out=>wb2); END behavioral; --------------------------------------------------------------------------- --Déclaration des librairies LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; USE work.projet.all; --Déclaration de l'entité ENTITY neuron IS PORT ( e1 : IN std_logic_vector(length downto 1); e2 : IN std_logic_vector(length downto 1); w0 : IN std_logic_vector(length DOWNTO 1); w1 : IN std_logic_vector(length DOWNTO 1); w2 : IN std_logic_vector(length DOWNTO 1); clk : IN std_logic; reset : IN std_logic; b : OUT std_logic_vector(length DOWNTO 1) ); END neuron; --Déclaration de l'architecture ARCHITECTURE behavioral OF neuron IS SIGNAL b2,b10,b20 : std_logic_vector(length DOWNTO 1); BEGIN cellule1 : mac PORT MAP (Sdata_in1=>e1,Sdata_in2=>w1,Sdata_in3=>w0,clk=>clk,reset=>reset,Sdata_out=>b2); cellule2 : mac PORT MAP (Sdata_in1=>e2,Sdata_in2=>w2,Sdata_in3=>b2,clk=>clk,reset=>reset,Sdata_out=>b); END behavioral; --------------------------------------------------------------------------- --Déclaration des librairies LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; USE work.projet.all; --Déclaration de l'entité ENTITY supervisor IS PORT ( e1 : IN std_logic_vector(length downto 1); e2 : IN std_logic_vector(length downto 1); S1 : IN std_logic_vector(length DOWNTO 1); clk : IN std_logic; reset : IN std_logic; b : OUT std_logic_vector(length DOWNTO 1) ); END supervisor; --Déclaration de l'architecture ARCHITECTURE behavioral OF supervisor IS SIGNAL bx00,bx10,Yso : std_logic_vector(length downto 1); SIGNAL wa0,wa1,wa2 : std_logic_vector(length downto 1); SIGNAL wb0,wb1,wb2 : std_logic_vector(length downto 1); SIGNAL wc0,wc1,wc2 : std_logic_vector(length downto 1); SIGNAL swa0,swa1,swa2 : std_logic_vector(length downto 1); SIGNAL swb0,swb1,swb2 : std_logic_vector(length downto 1); SIGNAL swc0,swc1,swc2 : std_logic_vector(length downto 1); SIGNAL ro0,ro1,ro2 : std_logic_vector(length downto 1); SIGNAL ro00,ro11,ro22 : std_logic_vector(length downto 1); SIGNAL ro000,ro111,ro222 : std_logic_vector(length downto 1); SIGNAL stp1,stp2,err : std_logic_vector(length downto 1); SIGNAL t_nuu0,t_nuu1,t_nuu2 : std_logic_vector(length downto 1); SIGNAL nuu0,nuu1,nuu2 : std_logic_vector(length downto 1); BEGIN b <= Yso; PROCESS(clk) VARIABLE temp : std_logic_vector(length*2 downto 1); BEGIN IF (clk'EVENT AND clk = '1') THEN IF (reset = '1') THEN ro0 <= (OTHERS => '0'); ELSE temp := err * Yso; ro0 <= temp(length*2) & temp(length+norm-1 DOWNTO norm+1); END IF; END IF; END PROCESS; --------------------------------------------------------------------------- PROCESS(clk) BEGIN IF (clk'EVENT AND clk = '1') THEN IF (reset = '1') THEN ro00 <= (OTHERS => '0'); ro11 <= (OTHERS => '0'); ro22 <= (OTHERS => '0'); ro000 <= (OTHERS => '0'); ro111 <= (OTHERS => '0'); ro222 <= (OTHERS => '0'); ELSE ro00 <= ro0; ro11 <= ro1; ro22 <= ro2; ro000 <= ro00; ro111 <= ro11; ro222 <= ro22; END IF; END IF; END PROCESS; --------------------------------------------------------------------------- PROCESS(clk) BEGIN IF (clk'EVENT AND clk = '1') THEN IF (reset = '1') THEN stp1 <= (OTHERS => '0'); stp2 <= (OTHERS => '0'); err <= (OTHERS => '0'); ELSE IF (e2 = allzeros) THEN stp1 <= (OTHERS => '0'); stp2 <= (OTHERS => '0'); err <= (OTHERS => '0'); ELSE stp1 <= step1; stp2 <= step2; err <= S1; END IF; END IF; END IF; END PROCESS; --------------------------------------------------------------------------- PROCESS(clk) BEGIN IF (clk'EVENT AND clk = '1') THEN IF (reset = '1') THEN t_nuu0 <= xnuu; t_nuu1 <= xnuu; t_nuu2 <= xnuu; ELSE IF ((ro0(length) = '0' AND ro00(length) = '0' AND ro000(length) = '0') OR (ro0(length) = '1' AND ro00(length) = '1' AND ro000(length) = '1')) THEN t_nuu0 <= nuu0 + stp1; ELSIF ((ro0(length) = '0' AND ro00(length) = '1' AND ro000(length) = '0') OR (ro0(length) = '1' AND ro00(length) = '0' AND ro000(length) = '1')) THEN t_nuu0 <= nuu0 + stp2; ELSE t_nuu0 <= nuu0; END IF; IF ((ro1(length) = '0' AND ro11(length) = '0' AND ro111(length) = '0') OR (ro1(length) = '1' AND ro11(length) = '1' AND ro111(length) = '1')) THEN t_nuu1 <= nuu1 + stp1; ELSIF ((ro1(length) = '0' AND ro11(length) = '1' AND ro111(length) = '0') OR (ro1(length) = '1' AND ro11(length) = '0' AND ro111(length) = '1')) THEN t_nuu1 <= nuu1 + stp2; ELSE t_nuu1 <= nuu1; END IF; IF ((ro2(length) = '0' AND ro22(length) = '0' AND ro222(length) = '0') OR (ro2(length) = '1' AND ro22(length) = '1' AND ro222(length) = '1')) THEN t_nuu2 <= nuu2 + stp1; ELSIF ((ro2(length) = '0' AND ro22(length) = '1' AND ro222(length) = '0') OR (ro2(length) = '1' AND ro22(length) = '0' AND ro222(length) = '1')) THEN t_nuu2 <= nuu2 + stp2; ELSE t_nuu2 <= nuu2; END IF; END IF; END IF; END PROCESS; --------------------------------------------------------------------------- PROCESS(clk) BEGIN IF (clk'EVENT AND clk = '0') THEN IF (reset = '1') THEN nuu0 <= xnuu; nuu1 <= xnuu; nuu2 <= xnuu; ELSE nuu0 <= t_nuu0; nuu1 <= t_nuu1; nuu2 <= t_nuu2; END IF; END IF; END PROCESS; --------------------------------------------------------------------------- couche1_1 : neuron PORT MAP (e1=>e1,e2=>e2,w0=>wa0,w1=>wa1,w2=>wa2,clk=>clk,reset=>reset,b=>bx00); couche1_2 : neuron PORT MAP (e1=>e1,e2=>e2,w0=>wb0,w1=>wb1,w2=>wb2,clk=>clk,reset=>reset,b=>bx10); --------------------------------------------------------------------------- couche2_1 : neuron PORT MAP (e1=>bx00,e2=>bx10,w0=>wc0,w1=>wc1,w2=>wc2,clk=>clk,reset=>reset,b=>Yso); --------------------------------------------------------------------------- compute_1 : mol PORT MAP (Sdata_in1=>bx00,Sdata_in2=>wc1,Sdata_in3=>err,clk=>clk,reset=>reset,Sdata_out=>ro1); compute_2 : mol PORT MAP (Sdata_in1=>bx10,Sdata_in2=>wc2,Sdata_in3=>err,clk=>clk,reset=>reset,Sdata_out=>ro2); --------------------------------------------------------------------------- ajust_1 : back_1 PORT MAP (by0=>bx00,by1=>bx10,nuu=>nuu0,err=>err,clk=>clk,reset=>reset, awc0=>wc0,awc1=>wc1,awc2=>wc2, wc0=>swc0,wc1=>swc1,wc2=>swc2); ajust_2 : back_2 PORT MAP (e1=>e1,e2=>e2,ro1=>ro1,ro2=>ro2,nuu1=>nuu1,nuu2=>nuu2,clk=>clk,reset=>reset, awa0=>wa0,awa1=>wa1,awa2=>wa2, awb0=>wb0,awb1=>wb1,awb2=>wb2, wa0=>swa0,wa1=>swa1,wa2=>swa2, wb0=>swb0,wb1=>swb1,wb2=>swb2); --------------------------------------------------------------------------- PROCESS(clk) BEGIN IF (clk'EVENT AND clk = '1') THEN IF (reset = '1') THEN wa0 <= xnuu; wa1 <= xnuu; wa2 <= xnuu; wb0 <= xnuu; wb1 <= xnuu; wb2 <= xnuu; wc0 <= xnuu; wc1 <= xnuu; wc2 <= xnuu; ELSE wa0 <= swa0; wa1 <= swa1; wa2 <= swa2; wb0 <= swb0; wb1 <= swb1; wb2 <= swb2; wc0 <= swc0; wc1 <= swc1; wc2 <= swc2; END IF; END IF; END PROCESS; END behavioral; ---------------------------------------------------------------------------

JANE Neuron Emulator VLSI design by Suresh kumar Devanathan