Hold Time in two clock domains

Two flipflops connected back to back could have a hold time failure and create a race condition. If the data from the first flipflop reaches the second at a time lesser than the hold time of the second after the clock edge the it can result in double clocking. Usually the equation is to have the MIN(Clk-Q) + MIN(logic delay between flops) > setuptime+skew+holdtime of the second flop This is the reason why specs talk about 2 inverter delays between flops.... be warned these are theoritical concepts , pratcially hold time is negligible for a flop I would like to know why the two flops have different clk frequencies........ -F

hi pushi321 If two FFs(with diff clocks) are intricated then thechances of setup time and hold time violations are more.That is why we have in general a unique clock and with even a small clock skew(not deliberate) is regretted.we have synchronizers for interfacing diff clocked ckts ,here the probab. of metastable state(caused due to setup and hold time vio) is very less. if FF1 is running at very high freq. then there may be many cases. data lapse with and without setup and hold violations. Generally we cannot comment on this.we need to know abt the clock freqs. Bye