Transistor Sizing (Intel Interview)

Hi all, What are the effects of making PMOS stronger than NMOS (by increasing W/L ratio of PMOS) and vice-versa in CMOS Inverter? How does the circuit behaves for 0->1 and 1->0 transition in each case? Thanks in advance, Ankit

Asked By: ankitcontact
On: Apr 4, 2005 4:23:55 PM

Comments(3)

this is the concept of skewing a gate I guess, if you make pmos stronger by incresing its size you get a high skewed inverter wherein the rising transition will happen faster than falling ...well the right way to say this is that for the inverter keep pmos size fixed and make nmos size half ...now we get a faster rising transition due to reduced parasitic capacitance but the falling transition will suffer as the nmos is half the size ... the same concept works the reverse when we do it for NMOS to get a low skewed inverter .. -firmy

Comment By: firmy
On: Apr 15, 2005 9:13:27 PM

one more DC analysis point of view is that the Vm changes. Vm=[(Vdd-|Vtp| +Vtn* sqrt(kn/kp))]/(1+sqrt(kn/kp)) as Kp is increased Vm falls down.So noise margin wont be VDD/2. Another one is the ckt will output an elegant one and a zero with a bondage Bye

Comment By: venkateshr
On: Apr 7, 2005 2:37:50 AM

Hi all, This is what I think: If you increase W/L of PMOS, Rp decreases, therefore, for 1->0 transition( at the input), that is the output would make a transition from low to high, that is delay would be tplh=0.69 Rp C would decrease.( vice-versa) Shefali

Comment By: shefaliw
On: Apr 5, 2005 1:16:19 PM

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