input switching voltage of 2 input nor gate

hi i want to know how to calculate the input switching voltage of a 2-input NOR gate constructed of identical sized n- and p- transisters with one input held high and both held high.how do the noise margin vary? what ramification does this have for multiple input gates

Asked By: nahla
On: Apr 4, 2005 8:20:56 AM

Comments(4)

respected sir, Could you please sent me e-mail about whole information about 8279 microprocessor ic. e-mail: anshulbandela@gmail.com Regards Anshul bandela

Comment By: anshul-vinu
On: Apr 2, 2011 4:01:44 AM

Nahla, By worst case condition sizing, what he meant was: suppose in 2 input NOR, u have 2 nmos in parallel, if both are on, effective resistance is Rn/2, but if one is on, effective resistance is Rn. So, worst case delay in this case would be for when one of two is on, i.e. for equivalent resistance Rn. that is why when we size for a 2 input NOR, the effective W/L of pull down network transistrs remains the same. Shefali

Comment By: shefaliw
On: Apr 5, 2005 1:19:39 PM

thank u v much Venkateshr so this changes "beta" and this affects the transister in saturation and linear region and how to find regions in DC transfer characteristics. "p.s:always size the trans for worst case conditions."i didnot anderstand this sentense

Comment By: nahla
On: Apr 5, 2005 9:57:23 AM

ignoring the body effect &nbspwe can make the trans. in series to be as a single with w/l divided by the no of trans(as u said all are eq sizes) and parallel trans as a single with w/l multiplied by the no of trans and then it is nothing but an inverter . p.s:always size the trans for worst case conditions.

Comment By: venkateshr
On: Apr 5, 2005 2:33:22 AM

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