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<-- Previous Next -- > TOPIC: verilog code 4 4-bit alu
Posted by: malik     4/2/2005 1:44:22 AM     Category: Verilog
Questions posted: 1         Comments Posted: 0
can anyone give me a 4-bit alu verilog code?

Posted by: elagab     12/6/2014 1:37:47 AM
Comments Posted:2       

iam master student at king fahad university in saudai arabia
you can send for me the code of 4 bit alu at my E-MAIL:
g201404020@kfupm.edu.sa


Posted by: elagab     12/6/2014 1:35:37 AM
Comments Posted:2       

please can you help me by supplying me alu code for 4 bits
i will be appreciate for you
thank you


Posted by: sesafheleng     9/20/2012 8:55:58 AM
Comments Posted:1       

This is an interesting code indeed.put a clock on the code bacause i want to see how the test bench will be like.Im to design a 4 bit ALU with @list 5 outputs using your code.try it using ModelSim PE software.


Posted by: srijoshi.092     11/15/2011 7:05:41 AM
Comments Posted:2       

hi nethra
i need alu which performs addn,subtraction, multiplication and division also with some two to three logical operaions like and, or.....


Posted by: nethra_k     11/10/2011 10:40:29 PM
Comments Posted:266       Questions Posted:2

hi Srikanth,
If you can specify the operations in ur ALU then it will be easy.


Posted by: srijoshi.092     11/10/2011 7:56:04 AM
Comments Posted:2       

i want verilog code for 16 bit alu... can any one help me plz its urgent....


Posted by: benzir_87     11/5/2009 10:52:22 PM
Comments Posted:1       

I need a 4 bit ALU layout within 12-11-1009


Posted by: Diving     8/20/2009 12:24:16 PM
Comments Posted:2       

Oh, I am using verilog for my code


Posted by: Diving     8/20/2009 12:23:41 PM
Comments Posted:2       

Hello I want to do an Alu with this characteristics:

An ALU that supports, addition, substraction, comparison of signed integers (+,-, <, >, ==), and boolean logic operations (!, &, |, ^).

If you have a similar code or any ideas how to start let me know, thank's.

Mario


Posted by: gumma raghu     10/20/2007 1:16:53 AM
Comments Posted:1       

can any one give me cpu code in verilog for 16-bit


Posted by: tobyli     4/11/2005 3:27:42 AM
Comments Posted:1       Questions Posted:1

Who can help me thanks alot
Write a VHDL model for the 4-bit ALU


Posted by: hsvijay     4/4/2005 2:46:09 AM
Comments Posted:10       

Hi ...

 Here I pasted a simple ALU , let me know if you need any further help:

module alu(a,b,cin,alu,carry,zero,ctl);

 input [3:0] a,b;         // port A,B
 input  cin ;             // carry input from carry flag register
 output [3:0] alu;        // the result
 output carry;            // carry output
 output zero ;            // zero output
 input [3:0] ctl ;        // functionality control for ALU
 wire [4:0] result;       // ALU result

 assign result = alu_out(a,b,cin,ctl);
 assign alu    = result[3:0];
 assign carry  = result[4] ;
 assign zero   = z_flag(result) ;

 function [4:0] alu_out;
   input  [3:0] a,b ;
   input        cin ;
   input  [3:0] ctl ;
   case ( ctl )
       4'b0000: alu_out=b;                  // select data on port B
       4'b0001: alu_out=b+4'b0001 ;         // increment data on port B
       4'b0010: alu_out=b-4'b0001 ;         // decrement data on port B
       4'b0011: alu_out=a+b;                // ADD without CARRY
       4'b0100: alu_out=a+b+cin;            // ADD with CARRY
       4'b0101: alu_out=a-b ;               // SUB without BORROW
       4'b0110: alu_out=a-b+(~cin);         // SUB with BORROW
       4'b0111: alu_out=a&b;                // AND
       4'b1000: alu_out=a|b;                // OR
       4'b1001: alu_out=a^b;                // EXOR
       4'b1010: alu_out={b[3:0],1'b0};      // Shift Left
       4'b1011: alu_out={b[0],1'b0,b[3:1]}; // Shift Right
       4'b1100: alu_out={b[3:0],cin};       // Rotate Left
       4'b1101: alu_out={b[0],cin,b[3:1]};  // Rotate Right
         default : begin
                     alu_out=9'bxxxxxxxxx;
                       $display("Illegal CTL detected!!");
                   end    
     endcase  /* {...,...,...} is for the concatenation.
                 {ADD_WITH_CARRY,SUB_WITH_BORROW}==2'b11 is used
                 to force the CARRY==1 for the increment operation */  
   endfunction // end of function "result"

  function z_flag ;
  input [4:0] a4 ;
    begin
      z_flag = ^(a4[0]|a4[1]|a4[2]|a4[3]) ; // zero flag check for a4
    end
  endfunction

endmodule
------------------------------------------

VJ




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