NAND Gate Optimization

I have to optimize 2 input nand gate such that Rise time and fall time comes equal for all input combinations (00,01,10,11). and ideas?

Asked By: smoke
On: Apr 1, 2005 2:08:18 AM

Comments(4)

To have equal rise and fall delay the resisistanceof pull up and pull down path have to be equal. In the worst case for pull up occurs when only one pmos is on. To achieve this make the width of your nmos as 2 and the witdth of pmos as 3.5.The size of pmos depends on the mobility ratio. It can vary from 2-3.5 depending on the process

Comment By: darad_jd
On: May 4, 2005 8:33:10 PM

Hi, As all we know that for a 2 inp NAND gate the structure is like this "two parallel pmos as pullup and two series nmos for pulldown and this makes that for the worst condition of having any 1 inp as 0 the rise time will depend on wp ,so have that to be that of the inverter(whose rise time is known or calculate that ) and for pulldown the worst condition is that two shd be turned on to sink so that have wn as twice that of the inverter's wn. in inverter wp=2.5 or three times that of wn for compensating the sluggish mobility of holes. wp and wn of inverter shd be selected according to the rise time and fall time u need. BYe

Comment By: venkateshr
On: Apr 4, 2005 2:40:06 AM

make wp = 2 to 3 times wn

Comment By: praveen_sam
On: Apr 1, 2005 11:26:12 AM

hi, i think you have to add an extra overhead to get this, because nothing comes out to be free. So to mentain equal rise and fall time in conentional CMOS technolgy, either both pull up tr. or one tr. must be on in any condition of 00,01 and 10. i will think again and tell you if found some more. if you found then tell also me. its an interresting question.

Comment By: sainiparvesh
On: Apr 1, 2005 6:57:46 AM

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