Odd Pulse Divider Design


How to design this Circuit? for an Input : 101010101 ( Clk) Output should be : 100010001 Thanks

Asked By: hemanthvlsi
On: Mar 13, 2005 10:14:22 PM

Comments(4)


just give the clk to T ff's clk ,ff's input is 1 and reset to 0. Bye

Comment By: venkateshr
On: Mar 14, 2005 12:47:42 AM

Oops sorry the waveform is distorted

Comment By: fresher@vlsi
On: Mar 14, 2005 12:34:46 AM

If output has to produce one pulse for every four clock cycles-use a mode four counter. But I think your question refers to high pulse for half a clock cycle and low for 1 and half clock cycles.For this generate a divided by two counter and "AND" it with clock signal. __ __ __ clk __| |__| |__| __ __ __ /2 __| |__ __| __ __ op __| |__ __ __|

Comment By: fresher@vlsi
On: Mar 14, 2005 12:33:49 AM

If output has to produce one pulse for every four clock cycles-use a mode four counter. But I think your question refers to high pulse for half a clock cycle and low for 1 and half clock cycles.For this generate a divided by two counter and "AND" it with clock signal. __ __ __ clk __| |__| |__| __ __ __ /2 __| |__ __| __ __ op __| |__ __ __|

Comment By: fresher@vlsi
On: Mar 14, 2005 12:32:59 AM

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