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<-- Previous Next -- > TOPIC: "Error loading design" error
Posted by: thomasc     3/4/2005 7:43:07 PM     Category: Verilog
Questions posted: 9         Comments Posted: 6
Hi,

I'd like to ask a question about "Error loading design" error. My module compiles fine without an error. However, when I tried to simulate it with a testbench for the module, ModelSim gives an error message, saying "Error loading design". I copied & pasted the error message and my code below. I haven't been able to find out how to fix this error. If you see any problem in my code, please let ne know.

Thanks.

vsim work.test_SaXSb
# vsim work.test_SaXSb
# Loading work.test_SaXSb
# Loading work.SaXSb
# ** Warning: (vsim-3009) [TSCALE] - Module 'SaXSb' does not have a `timescale directive in effect, but previous modules do.
#         Region: /test_SaXSb/X1
# ** Error: (vsim-3033) D:/ ....... /SaXSb.v(11): Instantiation of 'zero_check' failed. The design unit was not found.
#         Region: /test_SaXSb/X1
#         Searched libraries:
#             work
# Loading work.exp_elem
# ** Warning: (vsim-3009) [TSCALE] - Module 'exp_elem' does not have a `timescale directive in effect, but previous modules do.
#         Region: /test_SaXSb/X1/E1
# Loading work.alpha_elem
# ** Warning: (vsim-3009) [TSCALE] - Module 'alpha_elem' does not have a `timescale directive in effect, but previous modules do.
#         Region: /test_SaXSb/X1/A1
# Error loading design


module SaXSb (Sx_val, Sx_exp, Sa, Sb);

input [7:0] Sa, Sb;
output [7:0] Sx_val, Sx_exp;

wire [7:0] Sx_val, Sx_exp;
wire [7:0] Sa_temp, Sb_temp;

parameter mask = 8'h0F;

zero_check(Sx_val, Sx_exp, Sa, Sb);  // <= THIS IS LINE (11) WHERE THE ERROR OCCURED

exp_elem E1 (.exp_val(Sa_temp), .index(Sa));
exp_elem E2 (.exp_val(Sb_temp), .index(Sb));

assign Sa_temp = wraparound_check(Sa_temp);

assign Sa_temp = Sa_temp & mask; // mask out 4 unnecessary MSB's
alpha_elem A1 (.alpha_val(Sb_temp), .index(Sa_temp));
assign Sx_val = Sb_temp;
assign Sx_exp = Sa_temp;

task zero_check;
inout [7:0] x_val, x_exp;
input [7:0] a, b;
reg [7:0] x_val, x_exp;

begin
if ((a==0)||(b==0)) begin
x_val = 8'h00;
x_exp = 8'h10; //if a==0 and b==0, Sx_val and
disable SaXSb; // Sx-exp values should not be
      // modified by the codes below
end //if
end //begin

endtask

function wraparound_check;
input [7:0] a_temp;
begin
if (a_temp >= 15) wraparound_check = a_temp+1;
end
endfunction

endmodule

Posted by: sricharan     9/14/2010 5:02:22 AM
Comments Posted:32       Questions Posted:2

first declare timescale directive so that the warnings wont be der
second case the as above mention there should be  instance name then the syntax will work perfectly .


Posted by: lal87     3/8/2010 4:09:18 AM
Comments Posted:37       

i think its not a problem with the code.try the following thing:
http://vhdlguru.blogspot.com/2010/03/xilinx-error-simulator702-can-not-find.html


Posted by: sreenathv     6/22/2009 7:32:33 AM
Comments Posted:7       Questions Posted:1

hi thomasc

just gine an instance name to ur zero_check then it should be fine
zero_check zc1(Sx_val, Sx_exp, Sa, Sb);

Sreenath


Posted by: $---jay---$     5/6/2009 3:30:59 AM
Comments Posted:104       Questions Posted:1

zero_check(Sx_val, Sx_exp, Sa, Sb);  // <= THIS IS LINE (11) WHERE THE ERROR OCCURED

as like u said, the error is with the above line, the syntax for instantiation is,

module_name module_instance_name(signal_list);

in ur code, there is no instance_name....that may be the error....

or else, the module - zero_check may be deleted in ur project folder....


Posted by: sivubj     5/4/2009 2:15:06 AM
Comments Posted:2       

hi i am doing vlsi project that is i2c controller design
all my codes are correct and simulated in xlinx 9.1i and simulated, but i need simulating in modelsim
also i have modelsim 6.5a pe edition tool i am trying doing my project simulation in this modelsim  i complied all codes successfuly but while i am triying to simulate, facing #ERROR LOADING DESIGN CAN TELL ME ANY ONE WHAT MIGHT BE THE PROBLEM also re install it and the new license key


Posted by: navina     3/6/2005 5:45:09 AM
Comments Posted:2       

hi thomasc,
  may be your instantiation of your main module into the test bench may not be proper .
just verify it and then compile it once again.
ALL THE BEST

navina


Posted by: thomasc     3/5/2005 10:01:36 PM
Comments Posted:6       Questions Posted:9

ganeshts,
Here's a copy of the task "zero_check". You can see it out at the bottom portion of my code(above "function wraparound_check;")

===
task zero_check;
inout [7:0] x_val, x_exp;
input [7:0] a, b;
reg [7:0] x_val, x_exp;

begin
if ((a==0)||(b==0)) begin
x_val = 8'h00;
x_exp = 8'h10; //if a==0 and b==0, Sx_val and
disable SaXSb; // Sx-exp values should not be
              // modified by the codes below
end //if
end //begin

endtask


Posted by: thomasc     3/5/2005 9:59:21 PM
Comments Posted:6       Questions Posted:9

Hi ganeshts,
zero_check is a task defined at the bottom portion of the same module. I don't understand why it can't find the unit inside the same module. Do you have any idea?
Thanks!




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