vlsibank

Log in or Sign up.
Main EDA Embedded Systems ASIC FPGA VHDL Verilog CMOS Semiconductors DSP Mixed Signal Architecture Miscellaneous

<-- Previous Next -- > TOPIC: PMOS and NMOS
Posted by: shantha_rang     3/1/2005 1:39:46 PM     Category: CMOS
Questions posted: 5         Comments Posted: 2
Hi,
I have a questions. When we say PMOS takes care of passing Logic 1 and NMOS takes care of passing Logic 0, what exactly does it mean.
Thanks Shantha

Posted by: krishnat     3/7/2005 3:42:53 PM
Comments Posted:6       

NMOS needs a difference of Vt between its Gate and source for it to remain on. Assume you connect the gate and one of the remaining terminals(Source/Drain) to Vdd and tap the output out of the other terminal(let this be teminal O).
As soon as the voltage in terminal O reaches Vdd-Vt, the NMOS turns off and doesnot let O go any higher. hence the final outout value would be vdd-vt and not vdd.Hence you say NMOS is a poor conductor of a "1". The dual of this applies to PMOS.
Hope this helps.


Posted by: ashok_su424     3/1/2005 11:15:46 PM
Comments Posted:17       Questions Posted:1

Hi!

PMOS can pass "1"  truly and "0" no to complete extent,
similarily, NMOS can pass both "0"  truly and "1"
not to complete extent.

ashok.


Posted by: saidurbha     3/1/2005 9:29:29 PM
Comments Posted:1       Questions Posted:1

hi shanthi my view on ur question is as follows , generally pmos transistor is used for charging which can be considered as logic 1 as it is always connected to VDD , similarly nmos is used for discharging i,e logic 0  as it is connected to the VSS,hence thsi makes us to analyse pmos as good for logic 1 and nmos for logic 0 .




You have to be logged in to be able to post a comment. To login click here. First time? Sign up. It just takes a few minutes to sign up.

Login to access the site

  Username:
  Password:
   Signup Forgot Password?    

Users with most replies

   User
 No. of Replies
266
104
86
76
75
70
63
61
57