vhdl code for multiplier and accumulator

what type of multiplication algorithm are you planning to use? How many bits? floating point? is it asynchronous tranmission or synchronous tranmission? will it require an output register? will it require an output buffer? will it receive its operands one bit at a time, two bits at a time, or all bits at once? Can it be clocked? What type of logic are you planning, FPGA nand based? CMOS? Whats more important size, speed, or lifespan? Is error checking required? Is this standard binary, or something like BCD, graycode etc.? are the numbers signed or unsigned? if signed does it need to output the new sign?