In CMOS Inverter, if ternimals are interchanged

Thank you isiah, I had same opinion. I undertand layouts pretty well.

sorry i am not talking about buffer operation. what would happen when terminals of nmos and pmos interchanged ? If drain of pmos is connected to Vdd and its source is connected to source of nmos and drain of nmos is grounded ? THIS IS THE NORMAL CONDITION: normally the drain of the pmos is connected to VDD normally the drain of the nmos is connected to ground normally the source of the pmos is connected to the source of the nmos remember the current flows from drain to source, I know it seems backwards but that is the convention. Ok so you want to know what happens if the pmos is flipped upside down? instead of VDD ----> DRAIN ----> Pmos -----> Source ----> DRAIN -----> NMOS ------> Source we use: VDD -----> SOURCE ----> Pmos -----> DRAIN ----> DRAIN -----> NMOS ------> Source well in a word "NOTHING" nothing happens. Unlike the BJT the doping levels in a mosfet are the same throughout the device. So you could flip them at any time. The names Source and Drain are assigned after the circuit is built to describe the layout they dont mean anything about the transistor itself. Here is a picture of a pmos layout http://ece451web.groups.et.byu.net/cadence-help/pictures/t3pic9.jpg I am not sure if you know anything about layout so I will explain. The red area in the center is the transistor itself while the rest is the body. The source is on the right or left and so is the drain. As you can see there is no difference between the right and left sides of the device. It has horizontal symmetry which means the drain and the source are exactly the same.

Hi isiah, sorry i am not talking about buffer operation. what would happen when terminals of nmos and pmos interchanged ? If drain of pmos is connected to Vdd and its source is connected to source of nmos and drain of nmos is grounded ?

classic question, you want to swap the nmos for the pmos right? If you dont let me know. ok lets go through the situation where there is a 1 on in the input pmos is activate on low conditions so the pmos is off nmos is activated on high condition so the nmos is on so vdd's current flows through the nmos but gets blocked by the pmos. So the output attached in the middle will have a voltage of Vdd - Vnmos ok lets go through the situation where there is a 0 on in the input pmos is activate on low conditions so the pmos is on nmos is activated on high condition so the nmos is off so vdd's current gets blocked by the nmos but but flows through the pmos. So the output attached in the middle will have a voltage of Vpmos which is close to zero. so it looks like a buffer 0 --> 0 1 --> 1 with one key difference, the output wont be rail-to-rail anymore. So if Vdd = 5v and ground = 0v output high would equal = Vdd - Vnmos (or Vthn as it is typically written) output low would equal = Vpmos (or Vthp as it is typically written) So say output high would be around 4.5 volts and output low would be around .5 volts. This would be a badly designed buffer circuit, it would have the advantage that it uses two less transistors then a normal one but it would have a non-zero static dissipation which means it uses energy even when not being used, it would also lack rail-to-rail output. To be honest I can't think of a good use for this circuit.