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<-- Previous Next -- > TOPIC: fix the bug in the code
Posted by: naren17     6/17/2010 7:58:54 AM     Category: Verilog
Questions posted: 3         Comments Posted: 4
could any one help me to fix the code below?
here strobe1 is the input and when it is high the data from datain1 should enter buffer of memory(buffer) and also set the enable high at the same time!

module protocols(clk,
    strobe1,
    output enable1,
 datain1
   );
parameter data_bus =7;
parameter buffer_width=7;
parameter length =1'b1;
//input datain1;
input clk;
reg enable1;
reg seten;
input strobe1;
input [data_bus:0]datain1;
reg [buffer_width:0]buffer;
reg buff;
reg setenable;
always@(posedge clk)
begin
if(strobe1==1)
begin
if (buff==0)
begin
buffer<=datain1;
setenable <= length;
end
assign buff = length;
assign seten = setenable;
assign enable1 = seten;
end
end
endmodule

Posted by: kumarshravan     7/26/2010 5:01:48 AM
Comments Posted:8       

You should not use assign statement in ALWAYS block


Posted by: naren17     6/18/2010 12:13:15 PM
Comments Posted:4       Questions Posted:3

help please




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