FIR filter using Distributed Arithmetic

Main EDA Embedded Systems ASIC FPGA VHDL Verilog CMOS Semiconductors DSP Mixed Signal Architecture Miscellaneous

<-- Previous Next -- > TOPIC: FIR filter using Distributed Arithmetic

Posted by: Gagan1029 3/9/2010 3:25:55 PM Category: Architecture
Questions posted: 2 Comments Posted: 0

I am building a DA based FIR filter.
I am using the structure shown in the figure 2 in this application note

http://www.xilinx.com/ipcenter/catalog/logicore/docs/da_fir.pdf

If my LUT has a 4 bit address and using 3 shift-registers,

what should be the size of my shift-register? and the value of B?
can I use B=8 and three 8bit shift-registers? or should I use B=4 and three 4bit shift-registers???

please need some help as soon as possible

Posted by: rshrig 4/9/2010 3:51:23 AM
Comments Posted:32 Questions Posted:2

staff.kfupm.edu.sa/ITC/miali/Distributed%20Arithmetic.ppt

This is very good PPT on DA

rshrig@gmail.com

You have to be logged in to be able to post a comment. To login click here. First time? Sign up. It just takes a few minutes to sign up.

Signup Forgot Password?

Users with most replies

User

No. of Replies

$---jay---$

100

venkateshr

bharath_kt

muthu_kumar

praveen_sam

ngasm

jeppe

avvaru_theja

vikas