verilog code for 16:1 mux with a mod 10 counter


hi , Iam designing a parallel to serial converter.My input data is 10 bits and i am using a 16:1 mux with a mod 10 counter .Can somebody give an idea of verilog code for above specified condition. Thank you

Asked By: ruki
On: Feb 10, 2010 5:47:46 PM

Comments(1)



module Countermod10(clk, state, clr); parameter n = 4; parameter modCnt = 11; input clk, clr; output [n-1:0]state; reg [n-1:0]state; always@(posedge clk) if(clr) state <= 0; else state <= (state + 1) % modCnt; endmodule module mux16 ( i0,i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15,s3,s2,s1,s0,y); input i0,i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15; input s3,s2,s1,s0; output y; wire y; assign y = s3 ? (s2 ? (s1?(s0?i15:i14):(s0?i13:i12)):(s1?(s0?i11:i10) :(s0?i9:i8))) :(s2 ? (s1?(s0?i7:i6) : (s0?i5:i4)) : (s1?(s0?i3:i2):(s0?i1:i0))); endmodule
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