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<-- Previous Next -- > TOPIC: real in vhdl
Posted by: albasith786     1/26/2010 6:11:16 AM     Category: VHDL
Questions posted: 2         Comments Posted: 1
how to use real values in vhdl. for ex: 1.1 + 1.1
how to use real values in vector form.
plz help me

Posted by: lal87     3/9/2010 7:13:58 AM
Comments Posted:37       

real values are anot synthesizable.So avoid there usage.

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