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<-- Previous Next -- > TOPIC: pulse generator code
Posted by: sruthi_oct14     11/30/2009 1:49:35 AM     Category: Verilog
Questions posted: 1         Comments Posted: 0
hey , i have this code which works in three modes : one shot pulse generator, pulse generator and square wave generator. The code is synthesizing but there is something wrong with the output.could you please check what is wrong?

module timer_synth(reset, ceb, write, data_in, clk,
load, data_out
   );
input reset;
input ceb, write, load;
input [7:0] data_in;
input clk;
output data_out;
// to declare the control word
reg [2:0] control_word_register;
reg disable_CWR;
// to declare counter with 8 bits
reg [7:0] counter;
reg [7:0] latch_counter;
//reg data_out;
// flag for 1st clk pulse after loading in value of
// counter
reg flag1;
// flag for half count cycle
reg flag2;
wire [7:0]data_in;
// to write control word into counter
// for control_word, bit 2 represents enable, bit 1 and 0
// represent counter mode
// this also latches in the counter value
always @ (ceb or write or reset or load or disable_CWR
or data_in)
begin
if (~ceb & write & ~load & ~reset)
control_word_register = data_in [2:0];

else if (~ceb & ~write & load & ~reset)
latch_counter = data_in;

else if (ceb & ~reset)
begin
// reset the control word counter
control_word_register = 0;
// reset the latch_counter
latch_counter = 0;
end

else if (disable_CWR)
control_word_register[2] = 0;
end
// to count for counter
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
disable_CWR <= 0;
flag1 <= 0;
counter <= 0;
flag2 <= 0;
end
else
begin
if (control_word_register[2]) // counter is
// enabled
begin
if (control_word_register[1:0] == 2'b00)
// this is
// for one shot mode
begin
if (~flag1)
begin
counter <= latch_counter;
flag1 <= 1;
end
else
if (counter == 8'hff)
begin
// to stop counter for one shot
// mode

disable_CWR <= 1;
flag1 <= 0;
end
else
counter <= counter + 1;
end
else if (control_word_register[1:0] ==
2'b01) // this
// is for waveform generator
begin
if (~flag1)
begin
counter <= latch_counter;
flag1 <= 1;
end
else
begin
if (counter == 8'hff)
flag1 <= 0;
counter <= counter + 1;
end
end
else if (control_word_register[1:0] ==
2'b10) // this
// is for 50% duty cycle waveform
// generator
begin
if (~flag1)
begin
counter <= latch_counter;
flag1 <= 1;
end
else
begin
if (counter == {1'b0,
latch_counter[7:1]})
begin
flag2<=~flag2;
counter <= counter- 1;
end
else
if (counter == 0)
flag1 <= 0;
else
counter <= counter- 1;
end
end
end
else
begin
disable_CWR <= 0;
flag1<= 0;
flag2<= 0;
end
end

end
assign data_out = (((counter == 8'hff) & (control_word_register [1:0] ==
2'b00) & flag1) |
((counter == 8'hff) & (control_word_register [1:0] == 2'b01)) |
(flag2 & (control_word_register [1:0] == 2'b10)) );


endmodule

Posted by: sudhirkv     12/5/2009 8:36:39 AM
Comments Posted:33       Questions Posted:2

do u have a test bench to test this???

please specify which output is not coming......

what is that data in and data out.....

please make u r question clear




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