D Flip Flop/ Latch

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Posted by: pankcdac 9/30/2009 8:50:44 AM Category: Verilog
Questions posted: 4 Comments Posted: 0

Hi, can anyone tell me how to infer a D latch or D flip flop with input fixed to logic 1, i tried as follows

always @(posedge CE)
begin
if(CE)
begin
q <= 1'b1;
end
end

but when i synthesize this in tool it optimizes to simple VCC connected to q.
I used Lattice ispClassic tool for ispMACH family CPLD.

Posted by: kumarshravan 7/26/2010 5:10:36 AM
Comments Posted:8

U hav implemented FF to make it latch change always@(posedge CE) to always@(CE)
u can see o/p diff only at the start of Simulation but not later keep clk freq to around 1 MHz

Posted by: mod 3/31/2010 7:53:24 PM
Comments Posted:1 Questions Posted:1

if u need a FF then u can instantiate that particular FLOP look at the ID( like MUXF5 or MUXF6 in xilinx FPGA.. u need to check with lattice what they name it as). I am sure you can do with LUT's but not sure with FF though.

Posted by: svmc26 10/3/2009 3:08:56 AM
Comments Posted:2

output is tied to 1 ....
if input is fixed to logic one .. output is always 1 ..
I don't understand what exactly you want to implement...

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