vlsibank

Log in or Sign up.
Main EDA Embedded Systems ASIC FPGA VHDL Verilog CMOS Semiconductors DSP Mixed Signal Architecture Miscellaneous

<-- Previous Next -- > TOPIC: setup and hold tim
Posted by: sfriwblcii     8/20/2009 1:18:25 AM     Category: ASIC
Questions posted: 1         Comments Posted: 0
Why is the set up and hold time required at all....i mean where is this extratime helped in the circuit..can u explain w.r.t to the cmos structure of the Flip Flop...as in is that some cap requires that or something else which requires that

Posted by: premna     3/9/2010 7:40:49 AM
Comments Posted:1       

when setup time will be negative




You have to be logged in to be able to post a comment. To login click here. First time? Sign up. It just takes a few minutes to sign up.

Login to access the site

  Username:
  Password:
   Signup Forgot Password?    

Users with most replies

   User
 No. of Replies
$---jay---$
100
venkateshr
86
bharath_kt
77
muthu_kumar
76
praveen_sam
70
ngasm
66
jeppe
61
avvaru_theja
57
vikas
54