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<-- Previous Next -- > TOPIC: Verilog Code for wallace tree multiplier
Posted by: joj1982     4/13/2009 1:43:05 AM     Category: Verilog
Questions posted: 2         Comments Posted: 0
I am designing an ALU for a superscalar processor. I need a pipelined 32 bit/ 16 bit wallace tree multiplier. can any body guide me regarding this

Posted by: nethra_k     3/5/2012 12:27:05 AM
Comments Posted:266       Questions Posted:2

Hi Swamy,

Plz specify ur requirement.


Posted by: swamy1991     3/4/2012 11:45:03 PM
Comments Posted:1       

i want


Posted by: ananthan     4/9/2011 2:17:55 AM
Comments Posted:1       

vlsi


Posted by: bharath_kt     4/13/2009 10:23:16 AM
Comments Posted:75       Questions Posted:1

http://www.knowledgetreasure.com/selvam/weblog/53.html

Download the pdf file mentioned in the above link. It explains the wallace tree multiplier implementation and its Verilog implementation. It has the verilog code for wallace-tree based multiplier.

You need to login to this website and you can find the link for whitepaper on the left side of the page. Without logging on, you won't find whitepaper link. After entering white paper webpage, click electronics link, you will find the docuemnt under this category. It also has another document that discuss about its HDL implementation.




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