hi there.
i've been writing the verilog program using modelsim v6.1g. and everytime i got a warning and my waveform can't be display. and often, the systm will hang and sometimes, i can't re-simulate the program. May i know what could the problem is?
The warning display after simulation:# Loading work.SPI_try4_tb
# Loading work.SPI_RR4
# ** Warning: (vsim-3009) [TSCALE] - Module 'SPI_RR4' does not have a `timescale directive in effect, but previous modules do.
#         Region: /SPI_try4_tb/SPItb

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And following is the program i wrote, hopefully someone could point out the mistake i code.

module SPI_RR4(input wire SYS_CLK,input wire RESET,
              input wire SI,output reg SCK,output reg MISO);
             
  assign CPOL=1;
 
  initial
  begin
      if(CPOL==1)
     SCK=1;
     else if(CPOL==0);
     SCK=0;
  end
 
  always @ (posedge SYS_CLK or negedge SYS_CLK)
  begin
       #10 SCK=~SCK;
  end  

endmodule
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Thanks alot:)