Chnnel Width of CMOS current process technolo


is there any limitation to reduce the channel width, and lenth in ASIC chip? What is current micron process technology in CMOS, ASIC?

Asked By: muwassil
On: Feb 2, 2005 5:28:41 AM

Comments(3)



Hi by reducing the channel lenths and widths(if they are of the order of debrogli wave lenth of electrons) the quantum effects(like tunneling) will become dominant and the entire behavior of the charges will change which will definitely effect the device performance..............
Hi, The current P4 was developed on a 90nm fabrication line. The next chips are going to be of 65nm technology. As you decrease the channel width and other feature sizes, many new problems need to be accounted for. One of the them is the increase in the sub-threshold leakage current. Serious problems are being encountered and today, getting a chip out in 65nm technology is a challenge, however, we expect to have one ready by this year end.
Well I think that when you change the width and length of any transistor is your chip it will obviously change the amount of current flowing and thus change your entire design. Thus design your transistor for a reasonable W/L ratio.
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