clock divider without using any flipflops


My professor assigns me a homework to design a circuit that can divide clock rate half but "without using flipflops". In other words it must be design by useing combinational logic. I tried several ways but all of them can't lack of flipflops. -- ask sincerely for help

Asked By: binbin
On: Feb 19, 2004 9:58:11 AM

Comments(4)



simulate these code you will get frequency double. this is a structral description of two not gate and one xor gate.not gate is delay with 1/4 time of frequency time. //frequecy doubler module f2 (q,clk); input clk; output q; not #5 (O1, clk); not #5 (O2, O1); xor (q, O2,clk); endmodule //testbench module top; reg clk; wire q; f2 f2 (q, clk); initial begin clk = 1'b1; #100 $finish; end always #20 clk = ~clk; endmodule
Try using a Toggle register with the D input as the clock.
I trid this method before. it dosen't work, because the output of mux is always unknown without any initializing. i don't know how to initialize the combinaltional circuit.
This is the method i came up with...there might be many other ways of doing it... the method invloves use of a 2:1mux and an inverter. The select signal of the 2:1 mux is the CLK. One input to the mux(when selct is 0) is the output of the mux..and the other input to the mux(when the selct is 1) is the inverted signal of the output of the mux. Let me know if u have any questions on the method..
You have to be logged in to be able to post a comment. To login Click Here. First time? Signup It just takes a few minutes to sign up.
Members with Most Replies
Find Job Openings