difference between VERILOG and VHDL


Dear friend What is the difference between VHDL language and VERILOG language?????? why almost all ASIC companies used VERILOG is design language is their any specific reason for this ?????? rgs krishna

Asked By: mpkrishna
On: Dec 20, 2004 5:46:52 AM

Comments(5)



VHDL is based on Ada, for syntax. Verilog is based on C, for syntax. Verilog is not as strict as VHDL for syntax, which could lead to 'sloppy' coding practice. VHDL is more formal, Verilog is less formal. Verilog is much easier to learn than VHDL VHDL may be used to write code from the higher-order system level down to the gate level. Verilog is inefficient at writing system level code, but may be used to write code down to sub-gate levels (the newer SystemVerilog may solve this problem of system level coding). Neither is used to model transistors/diodes/resistors/etc. Both may be used to model behavior as well as discrete gate-level logic. There is a new 'analog' version of Verilog that is either under development, or is available. There is no analogVHDL.
how can we assign a set of memory to store the various programmes through the ports in vlsi design
What is the differenc between Verilio & VHDL? Which is more easy to use?
dear friend's What is the difference between VHDL language and VERILOG language?????? why almost all ASIC companies used VERILOG is design language is their any specific reason for this ?????? mukesh
Both r RTL( register tranfer level)coding only. verilog is similar to c language. so most of the companies preferring verilog.
You have to be logged in to be able to post a comment. To login Click Here. First time? Signup It just takes a few minutes to sign up.
Members with Most Replies
Find Job Openings