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<-- Previous Next -- > TOPIC: Charge sharing
Posted by: sekhar     12/12/2004 1:09:12 AM     Category: CMOS
Questions posted: 37         Comments Posted: 25
Can anyone let me know what is charge sharing in CMOS(digital) circuits.


Posted by: ashok_su424     12/16/2004 3:34:34 AM
Comments Posted:17       Questions Posted:1

charge sharing is a general phenomena.
where in charge gets shared between two parts of the circuit.

What anssprasad said is one example for that.


Posted by: anssprasad     12/15/2004 10:16:04 AM
Comments Posted:1       Questions Posted:1

charge sharing is a phenomenon found in clocked cmos logic and dynamic cmos logic.

in the precharge mode the output capacitance is charged to Vdd. now if the logic block has top transistors in the on state and the bottom ones(those which are nearer to Vss) in off state then during the evaluate mode the charge on the output capacitance is shared among the capacitances or transistors which are in the on state. this is charge sharing due to which the output voltage degrades below the logic threshold sometimes.

for better pictorial explanation see Introduction to cmos VLSI design by p.uyemura wiley publications


Posted by: sekhar     12/14/2004 2:45:26 PM
Comments Posted:25       Questions Posted:37

Thank you


Posted by: red     12/13/2004 6:37:25 PM
Comments Posted:2       

Sekhar,

I will share with you what little that I know.

Charge sharing causes a voltage stored on the BUS line to degrade. So if a BUS's cap. is Cb and the voltage level is Vdd then we get the charge on the bus as Qb = Cb.Vdd.

when this BUS is sampled (to read data for example) then the voltage on that BUS s degraded by the Cs term in the equation below. (Cs is smapling Ckt capacitance). So Cs has to be made small in order to preserve original Vb (voltage on BUS).

Vb = Qt/Ct = (Cb*Vdd)/(Cb+Cs)




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